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參數(shù)資料
| 型號： | THS1009IDARG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，2個模擬輸入，8 MSPS的同步采樣模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 235K |
| 代理商： | THS1009IDARG4 |
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SLAS287A
–
AUGUST 2000
–
REVISED DECEMBER 2002
www.ti.com
26
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
The THS1009 features two analog input channels. These can be configured for either single-ended or differential
operation. Figure 33 shows a simplified model, where a single-ended configuration for channel AINP is selected. The
reference voltages for the ADC itself are V
REFP
and V
REFM
(either internal or external reference voltage). The analog
input voltage range is between V
REFM
to V
REFP
. This means that V
REFM
defines the minimum voltage and V
REFP
defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage
V
REFM
of 1.5 V and the voltage V
REFP
of 3.5 V (see also section Reference Voltage). The resulting analog input
voltage swing of 2 V can be expressed by:
VREFM
AINP
VREFP
10-Bit
ADC
VREFP
VREFM
AINP
Figure 33. Single-Ended Input Stage
A differential operation is desired for many applications due to better signal-to-noise ration. Figure 34 shows a
simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The differential
operation mode provides in terms of performance benefits over the single-ended mode and is therefore
recommended for best performance. The THS1009 offers 1 differential analog input and in the single-ended mode
2 analog inputs. If the analog input architecture is differential, common-mode noise and common-mode voltages can
be rejected. Additional details for both modes are given below.
10-Bit
ADC
VREFP
VREFM
AINP
Σ
–
VADC
AINM
+
Figure 34. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, V
ADC
, which is applied at the input
of the ADC is the difference between the input AINP and AINM. The voltage V
ADC
can be calculated as follows:
VADC
ABS(AINP
–
AINM)
An advantage to single-ended operation is that the common-mode voltage
VCM
AINM
AINP
2
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND
AINM, AINP
AVDD
1 V
VCM
4 V
(1)
(2)
(3)
(4)
(5)
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