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參數(shù)資料
| 型號： | THS1009IDARG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，2個模擬輸入，8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 20/31頁 |
| 文件大?。?/td> | 235K |
| 代理商： | THS1009IDARG4 |
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SLAS287A
–
AUGUST 2000
–
REVISED DECEMBER 2002
www.ti.com
20
Control Register 1, Write Only (see Table 11)
BIT11
0
BIT 10
1
BIT 9
BIT 8
OFFSET
BIT 7
BIN/2s
BIT 6
R/W
BIT 5
RES
BIT 4
RES
BIT 3
RES
BIT 2
RES
BIT 1
SRST
BIT 0
RESET
RESERVED
Table 11. Control Register 1 Bit Functions
BITS
RESET
VALUE
NAME
FUNCTION
0
0
RESET
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
To bring the device out of RESET, a 0 has to be written into this bit.
1
0
SRST
Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the
configuration cycle.
2, 3
0,0
RES
Reserved
4
1
RES
Reserved
5
1
RES
Reserved
6
0
R/W
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR
.
When
bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
7
0
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format.
Refer to Table 2 through Table 5.
8
0
OFFSET
Offset cancellation mode
Bit 8 = 0
→
normal conversion mode
Bit 8 = 1
→
offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-
sion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the offset error.
9
0
RESERVED
Always write 0.
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