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參數(shù)資料
| 型號： | THS1009IDARG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，2個模擬輸入，8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 235K |
| 代理商： | THS1009IDARG4 |
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SLAS287A
–
AUGUST 2000
–
REVISED DECEMBER 2002
www.ti.com
14
DETAILED DESCRIPTION
Reference Voltage
The THS1009 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and
REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the
upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS1009 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Converter
The THS1009 uses a 10-bit pipelined multistaged architecture which achieves a high sample rate with low power
consumption. The THS1009 distributes the conversion over several smaller ADC sub-blocks, refining the conversion
with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion
requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier
(SHA) within each of the stages permits the first stage to operate on a new input sample while the second through
the eighth stages operate on the seven preceding samples.
Conversion
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion
is started with every falling edge of the applied clock signal. The conversion values are available at the output with
a latency of 5 clock cycles.
SYNC
In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK after
a SYNC reset. This is due to the latency of the pipeline architecture of the THS1009.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1
shows the maximum conversion rate for the different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
8 MSPS
2 single-ended channels
2
4 MSPS
1 differential channel
1
8 MSPS
The maximum conversion rate per channel, fc, is given by:
fc
8 MSPS
# channels
Continuous Conversion Mode
During conversion the ADC operates with a free running external clock signal applied to the input CONV_CLK. With
every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding
read signal. The THS1009 offers up to two analog inputs to be selected. It is important to provide the channel
information to the system; this means knowing which channel is available to the databus. To maintain this channel
integrity, the THS1009 has an output signal SYNC, which is always active low if the data of channel 1 is applied to
the databus.
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