參數(shù)資料
型號(hào): THS1009IDARG4
廠商: Texas Instruments, Inc.
英文描述: 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
中文描述: 10位,2個(gè)模擬輸入,8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 19/31頁(yè)
文件大?。?/td> 235K
代理商: THS1009IDARG4
SLAS287A
AUGUST 2000
REVISED DECEMBER 2002
www.ti.com
19
ANALOG INPUT CHANNEL SELECTION
The analog input channels of the THS1009 can be selected via bits 3 to 7 of control register 0. One single channel
(single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between
single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel
is selected. Table 9 shows the possible selections.
Table 9. Analog Input Channel Configurations
BIT 7
SCAN
BIT 6
DIFF1
BIT 5
DIFF0
BIT 4
CHSEL1
BIT 3
CHSEL0
DESCRIPTION OF THE SELECTED INPUTS
0
0
0
0
0
Analog input AINP (single ended)
0
0
0
0
1
Analog input AINM (single ended)
0
0
0
1
0
Reserved
0
0
0
1
1
Reserved
0
0
1
0
0
Differential channel (AINP
AINM)
0
0
1
0
1
Reserved
Autoscan two single ended channels: AINP, AINM, AINP,
Reserved
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
Reserved
1
0
1
0
1
Reserved
1
0
1
1
0
Reserved
1
1
0
0
1
Reserved
0
0
1
1
0
Reserved
0
0
1
1
1
Reserved
1
0
0
0
0
Reserved
1
0
1
0
0
Reserved
1
0
1
1
1
Reserved
1
1
0
0
0
Reserved
1
1
0
1
0
Reserved
1
1
0
1
1
Reserved
1
1
1
0
0
Reserved
1
1
1
0
1
Reserved
1
1
1
1
0
Reserved
1
1
1
1
1
Reserved
Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in
Table 10.
Table 10. Test Mode
BIT 9
TEST1
BIT 8
TEST0
OUTPUT RESULT
0
0
Normal mode
0
1
VREFP
1
0
((VREFM)+(VREFP))/2
VREFM
1
1
Three different options can be selected. This feature allows support testing of hardware connections between the
ADC and the processor.
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