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參數(shù)資料
| 型號(hào)： | THS1009IDARG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，2個(gè)模擬輸入，8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 25/31頁 |
| 文件大小： | 235K |
| 代理商： | THS1009IDARG4 |
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SLAS287A
–
AUGUST 2000
–
REVISED DECEMBER 2002
www.ti.com
25
Write Timing (using R/W, CS0-controlled)
Figure 32 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1009 can be performed
irrespective of the conversion clock signal CONV_CLK.
D(0
–
11)
10%
10%
10%
10%
90%
90%
90%
tw(CS)
óóóó
óóóó
óóóó
tsu(R/W)
th(R/W)
tsu
th
RD
R/W
CS1
CS0
Figure 32. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CS0-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tsu(R/W)
tsu
th
th(R/W)
tw(CS)
Setup time, R/W stable to last CS valid
0
Setup time, data valid to first CS invalid
5
ns
Hold time, first CS invalid to data invalid
2
ns
Hold time, first CS invalid to R/W change
5
ns
Pulse duration, CS active
10
ns
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