參數(shù)資料
型號(hào)： THS1009IDARG4
廠商： Texas Instruments, Inc.
英文描述： 10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
中文描述： 10位，2個(gè)模擬輸入，8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 22/31頁(yè)
文件大?。?/td> 235K
代理商： THS1009IDARG4
SLAS287A
–
AUGUST 2000
–
REVISED DECEMBER 2002
www.ti.com
22
Read Timing (using RD, RD-controlled)
Figure 29 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input
RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external
signal of CS0, CS1, and RD which becomes valid.
óóóóó
óóóóó
90%
90%
90%
10%
tw(RD)
tsu(CS)
th(CS)
ta
th
td(CSDAV)
CS0
CS1
WR
RD
D(0
–
9)
DATA_AV
10%
Figure 29. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
ta
td(CSDAV)
th
th(CS)
tw(RD)
Setup time, RD low to last CS valid
0
ns
Access time, last CS valid to data valid
0
10
ns
Delay time, last CS valid to DATA_AV inactive
12
ns
Hold time, first CS invalid to data invalid
0
5
ns
Hold time, RD change to first CS invalid
5
ns
Pulse duration, RD active
10
ns
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