參數(shù)資料
型號(hào)： TDA9112A
廠商： STMICROELECTRONICS
元件分類： 偏轉(zhuǎn)
英文描述： HORIZ/VERT DEFLECTION IC, PDIP32
封裝： PLASTIC, SDIP-32
文件頁(yè)數(shù)： 31/60頁(yè)
文件大小： 831K
代理商： TDA9112A
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9.3.4
PLL2
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a cer-
tain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase correc-
tions, like e.g., parallelogram. The PLL2 is fast
enough to be able to follow the dynamism of phase
modulation, this speed is strongly related to the
value of the capacitor on HPLL2C. The PLL2 con-
trol current (see Figure 7) is significantly increased
during discharge of vertical oscillator (during verti-
cal retrace period) to be able to make up for the
difference of dynamic phase at the bottom and at
the top of the picture. The PLL2 control current is
integrated on the external filter on pin HPLL2C to
obtain smoothed voltage, used, in comparison
with VCO ramp, as a threshold for H-drive rising
edge generation.
As both leading and trailing edges of the H-drive
signal in the Figure 7 must fall inside the rising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while consider-
ing the application frequency range and H-flyback
duration. The Figure 7 also shows regions for rising
and falling edges of the H-drive signal on HOut pin.
As it is forced high during the H-flyback pulse and
low during the VCO discharge period, no edge
during these two events takes effect.
The flyback input configuration is in Figure 8.
9.3.5
Dynamic PLL2 phase control
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchroniza-
tion). Inside the device, the threshold VS(0) is com-
pared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 14
and Chapter 7 - page 22. The correction
waveforms have no effect in vertical middle of the
screen (for middle vertical position). As they are
summed, their effect on the phase tends to reach
maximum span at top and bottom of the picture.
As all the components of the resulting correction
waveform (linear for parallelogram correction, pa-
rabola of 2nd order for Pin cushion asymmetry cor-
rection and half-parabolas of 4th order for corner
corrections independently at the top and at the
bottom) are generated from the output vertical de-
flection drive waveform, they all track with real ver-
tical amplitude and position, thus being fixed on
the screen. Refer to Chapter 8 - page 27 for details
on IC-bus controls.
Figure 7. Horizontal timing diagram
Figure 8. HFly input configuration
H-fly-back
PLL2
H-drive
current
control
+
-
(on HOut)
tS
H-drive
region
H-drive
region
inhibited
tS: HOT storage time
H-Osc
7/8TH
TH
max.
med.
min.
H-sync
(polarized)
REF1
min
max
(IC)
max.
med.
min.
PLL1 lock
(internal)
(VCO)
PLL2
PLL1
control
ON
forced high
forced low
OFF
ON
HPOS
VHOThrHi
VHOThrLo
VThrHFly
VHPosF
VS(0)
tph(max)
tHph
tHoff
~20k
~500
int.
ext.
HFly
GND
12
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