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參數(shù)資料
| 型號(hào)： | TDA9112A |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 21/60頁(yè) |
| 文件大?。?/td> | 831K |
| 代理商： | TDA9112A |
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Obsolete
Product(s)
- Obsolete
Product(s)
TDA9112A
28/60
Note 65: With exception of
HDUTY and BREF adjustments data that can take effect instantaneously if switches
HDutySyncV and B+SyncV are at 0, respectively.
Note 66: In Read Mode, the device always outputs data of the status register, regardless of sub address previously
selected.
Note 67: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
10
HSIZE
Horizontal size
1
0
000
00
0
11
Reserved
PCAC
Pin cushion asymmetry correction
1
000
00
0
12
Reserved
PARAL
Parallelogram correction
1
000
00
0
13
Reserved
TCAC
Top corner asymmetry correction
1
000
00
0
14
Reserved
BCAC
Bottom corner asymmetry correction
1
000
00
0
15
VDyCorPol
0: ”
∪"
VDC-AMP
Vertical dynamic correction
1
000
00
0
16
XRayReset
0: No effect
1: Reset
VSyncAuto
1: On
VSyncSel
0:Comp
1:Sep
SDetReset
0: No effect
1: Reset
PLL1Pump
1,1: Fastest
0,0: Slowest
PLL1InhEn
1: On
HLockEn
1: On
17
TV
0: Off(67)
TH
0: Off(67)
TVM
0: Off(67)
THM
0: Off(67)
BOHEdge
0: Falling
HBOutEn
0: Disable
VOutEn
0: Disable
BlankMode
1: Perm.
18
Reserved
0:
HVDC-HSHAP
HVDyCor horizontal shape
0
000
00
0
19
Reserved
0:
EWSC
East-West S-correction
1
000
00
0
1A
Reserved
0:
EWWC
East-West W-correction
1
000
00
0
1B
Reserved
0:
HEHTG
Horizontal EHT compensation gain
0
000
00
0
1C
Reserved
0:
VEHTG
Vertical EHT compensation gain
0
000
00
0
1D
Reserved
0:
VSAG
Vertical size after-gain
1
110
00
0
1E
Reserved
0:
VPOF
Vertical position offset
1
000
00
0
1F
ThrBlsense
0: High
BMute
0: Off
BSafeEn
0: Disable
EWTrHSize
0: Tracking
Ident
0: No effect
HLockSpeed
0: Slow
HVDyCorPol
0: ”
∪"
HDCFlatEn
0: Disable
READ MODE (SLAVE ADDRESS = 8D)
XX(66
)
HLock
0: Locked
1: Not locked
VLock
0: Locked
1: Not lock.
XRayAlarm
1: On
0: Off
Polarity detection
Sync detection
HVPol
1: Negative
VPol
1: Negative
VExtrDet
0: Not det.
HVDet
0: Not det.
VDet
0: Not det.
Table 8. IC-bus control registers
Sad
D7
D6
D5
D4
D3
D2
D1
D0
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