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參數(shù)資料
| 型號： | TDA9112A |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 831K |
| 代理商： | TDA9112A |
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Obsolete
Product(s)
- Obsolete
Product(s)
TDA9112A
27/60
8 IC-BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode. The control register map is given in
Table .
Bold weight denotes default value at Power-On-Reset.
IC-bus data in the adjustment register is buffered and internally applied with discharge of the vertical os-
cillator (65).
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.
Table 8. IC-bus control registers
Sad
D7
D6
D5
D4
D3
D2
D1
D0
WRITE MODE (SLAVE ADDRESS = 8C)
00
HDutySyncV
1: Synchro.
0: Asynchro.
HDUTY
Horizontal duty cycle
0
01
HPOS
Horizontal position
1
0
000
00
0
02
HMoiréMode
1: Separated
0: Combined
HMOIRE
Horizontal moiré amplitude
0
000
00
0
03
B+SyncV
0: Asynchro.
BREF
B+reference
1
000
00
0
04
HDyCorTr
0: Not active
HVDC-HAMP
HVDyCor horizontal amplitude
1
000
00
0
05
HDyCorPh
1: Middle
0: Start
HVDC-HPH
HVDyCor horizontal phase
1
000
00
0
06
BOutPol
0: Type N
HVDC-VAMP
HVDyCor vertical amplitude
1
000
00
0
07
BOutPh
0: H-flyback
1: H-drive
VSIZE
Vertical size
1
000
00
0
08
EWTrHFr
0: No tracking
VPOS
Vertical position
1
000
00
0
09
Reserved
SCOR
S-correction
1
000
00
0
0A
Reserved
CCOR
C-correction
1
000
00
0
0B
Reserved
VMOIRE
Vertical moiré amplitude
0
000
00
0
0C
Reserved
PCC
Pin cushion correction
1
000
00
0
0D
Reserved
KEYST
Keystone correction
1
000
00
0
0E
Reserved
TCC
Top corner correction
1
000
00
0
0F
Reserved
BCC
Bottom corner correction
1
000
00
0
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