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參數(shù)資料
| 型號(hào)： | TDA9112A |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 28/60頁(yè) |
| 文件大小： | 831K |
| 代理商： | TDA9112A |
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VExtrDet, VPol, HVPol). The device is equipped
with an automatic mode (switched on or off by
VSyncAuto IC-bus bit) that also uses the detec-
tion information.
Figure 2. Horizontal sync signal
9.2.2
Sync. presence detection flags
The sync. signal presence detection flags in the
status register (VDet, HVDet, VExtrDet) do not
show in real time the presence or absence of cor-
responding sync. signal. They are latched to 1 as
soon as a single sync. pulse is detected. In order
to reset them to 0 (all at once), a 1 must be written
into SDetReset IC-bus bit, the reset action taking
effect with ACK bit of the IC-bus transfer to the
register containing SDetReset bit. The detection
circuits are ready to capture another event (pulse).
See Note 68.
Figure 3. Extraction of V-sync signal from H/V-sync signal
9.2.3
MCU controlled sync. selection mode
IC-bus bit VSyncAuto is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the SDetReset bit to 1 and an appro-
priate delay, to obtain a true information of the sig-
nals applied, reads and evaluates this information
and controls the vertical signal selector according-
ly. The MCU has no access to polarity inverters,
they are controlled automatically.
See also chapter Chapter 8 - page 27.
9.2.4
Automatic sync. selection mode
IC-bus bit VSyncAuto is set to 1. In this mode, the
device itself controls the IC-bus bits switching the
polarity inverters (HVPol, VPol) and the vertical
sync. signal selector (VSyncSel), using the infor-
mation provided by the detection circuitry. If both
extracted and pure vertical sync. signals are
present, the one already selected is maintained.
No intervention of the MCU is necessary.
Positive
Negative
TH
tPulseHSyn
H/V-sync
Integration
Extracted
TH
V-sync
Internal
tPulseHSyn
textrV
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