參數(shù)資料
型號(hào)： TDA9112A
廠商： STMICROELECTRONICS
元件分類： 偏轉(zhuǎn)
英文描述： HORIZ/VERT DEFLECTION IC, PDIP32
封裝： PLASTIC, SDIP-32
文件頁(yè)數(shù)： 27/60頁(yè)
文件大?。?/td> 831K
代理商： TDA9112A
Obsolete
Product(s)
- Obsolete
Product(s)
TDA9112A
33/60
9 OPERATING DESCRIPTION
9.1
Supply and control
9.1.1
Power supply and voltage references
The device is designed for a typical value of power
supply voltage of 12 V.
In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of
VCC
is monitored. See Figure 1 and electrical spec-
ifications. At switch-on, the device enters a “nor-
mal operation” as the supply voltage exceeds VC-
CEn
and stays there until it decreases bellow VC-
CDis
. The two thresholds provide, by their differ-
ence, a hysteresis to bridge potential noise. Out-
side the “normal operation”, the signals on HOut,
BOut
and VOut outputs are inhibited and the IC-
bus interface is inactive (high impedance on SDA,
SCL
pins, no ACK), all IC-bus control registers be-
ing reset to their default values (see Chapter 8 -
page 27
). The stop of HOut and BOut drive signals
when the VCC falls from normal operation below
VCCDis
is not instantaneous. It is only a trigger
point of Soft Stop mechanism (see Subsection 9.3.7-
page 38
).
Figure 1. Supply voltage monitoring
Internal thresholds in all parts of the circuit are de-
rived from a common internal reference supply
VRefO
that is lead out to RefOut pin for external fil-
tering against ground as well as for external use
with load currents limited to IRefO. The filtering is
necessary to minimize interference in output sig-
nals, causing adverse effects like e.g. jitter.
9.1.2
IC-bus control
The IC-bus is a 2 line bidirectional serial commu-
nication bus introduced by Philips. For its general
description, refer to corresponding Philips IC-bus
specification.
This device is an IC-bus slave, compatible with
fast (400kHz) IC-bus protocol, with write mode
slave address of 8Ch (read mode slave address
8Dh). Integrators are employed at the SCL (Serial
Clock) input and at the input buffer of the SDA (Se-
rial Data) input/output to filter off the spikes up to
50ns.
The device supports multiple data byte messages
(with automatic incrementing of the IC-bus subad-
dress) as well as repeated Start Condition for IC-
bus subaddress change inside the IC-bus mes-
sages. All IC-bus registers with specified IC-bus
subaddress are of WRITE ONLY type, whereas
the status register providing a feedback informa-
tion to the master IC-bus device has no attributed
IC-bus subaddress and is of READ ONLY type.
The master IC-bus device reads this register
sending directly, after the Start Condition, the
READ device IC-bus slave address (8Dh) fol-
lowed by the register read-out, NAK (No Acknowl-
edge) signal and the Stop Condition.
For the IC-bus control register map, refer to Chap-
ter 8 - page 27
.
9.2
Synchronization processor
9.2.1
Synchronization signals
The device has two inputs for TTL-level synchroni-
zation signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On H/
HVSyn
input, pure horizontal or composite horizon-
tal/vertical signal is accepted. On VSyn input, only
pure vertical sync. signal is accepted. Both posi-
tive and negative polarities may be applied on ei-
ther input, see Figure 2. Polarity detector and pro-
grammable inverter are provided on each of the
two inputs. The signal applied on H/HVSyn pin, af-
ter polarity treatment, is directly lead to horizontal
part and to an extractor of vertical sync. pulses,
working on principle of integration, see Figure 3.
The vertical sync. signal applied to the vertical de-
flection processor is selected between the signal
extracted from the composite signal on H/HVSyn in-
put and the one applied on VSyn input. The selec-
tor is controlled by VSyncSel IC-bus bit.
Besides polarity detection, the device is capable of
detecting presence of sync. signals on each of the
inputs and at the output of vertical sync. extractor.
The information from all detectors is provided in
the IC-bus status register (5 flags: VDet, HVDet,
Normal operation
hysteresis
t
Disabled
V(Vcc)
VCC
VCCEn
VCCDis
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