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參數(shù)資料
| 型號： | TDA1315H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital audio input/output circuit DAIO |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大?。?/td> | 411K |
| 代理商： | TDA1315H |
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1995 Jul 17
27
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Notes
1.
2.
Pull-up specified at input to V
SS
, pull-down specified at input to V
DD
.
Most timing specifications are related to clock periods. Two basic periods are of importance:
a) T
c
, this is the internal clock period of the TDA1315H being
1
128
f
s
seconds.
b) T
s
, this is the system clock period such as SYSCLKI or SYSCLKO, being
1
256
f
s
or
1
384
f
s
seconds.
c) It should be noted that in the receive mode clock frequencies are only reliable when the TDA1315H is in-lock.
In the transmit mode, when SYSCLKI is 384f
s
and 30% or 70% duty cycle: t
HD;DT
is 0.43T
c
minimum.
This time strongly depends on the external decoupling capacitor connected to V
ref
(pin 2). When the capacitor is
initially empty, it must first be charged before the oscillator can start.
Internally this resistor will be connected between RC
fil
and V
ref
, when there is no signal on the selected IEC input in
receive mode, or when the oscillator is turned off. This is to prevent the oscillator to drift to extreme low or high
frequencies. See also Chapter “Characteristics”with regards to f
oclk(l)
and f
oclk(u)
.
These figures are theoretical limits for the TDA1315H. In the application, the maximum frequencies at f
s
= 48 kHz
will be fixed. Consequently f
iclk
= 12.288 MHz (CLKSEL = 1) and f
iclk
= 18.432 MHz (CLKSEL = 0).
These frequencies mean that the TDA1315H is guaranteed to lock in the range f
s
= 31.5 to 48.5 kHz over the whole
supply voltage range and specified temperature range.
These are the limit frequencies that the internal oscillator may reach under extreme conditions when the VCO input
(pin RC
fil
) would be controlled far beyond its normal tuning range. An internal resistor however, prevents that these
frequencies can be reached when there is no signal to lock-on to. See also Chapter “Characteristics” regarding R
tr
.
3.
4.
5.
6.
7.
8.
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E” The number of this quality specification can be found in the “Quality Reference
Pocketbook” The pocketbook can be ordered using the code 9398 510 34011.
R
tr
transmission-gate
resistor
V
ref
= 2.1 V; V
DD
= 5 V;
note 5
1
M
RC
int
OUTPUT
(
PIN
44)
C
o
parallel output
capacitance
output charge current
output charge current
5
pF
I
ch(fr)
I
ch(ph)
SYSCLKI
INPUT
(
PIN
39);
TRANSMIT MODE
; V
DD
= 3.4
TO
5.5 V
f
iclk
input clock frequency
frequency detector loop
phase detector loop
±
12
±
24
μ
A
μ
A
CLKSEL = 1; note 6
CLKSEL = 0; note 6
16
(6)
24
(6)
MHz
MHz
SYSCLKO
OUTPUT
(
PIN
40);
RECEIVE MODE
; V
DD
= 3.4
TO
5.5 V
f
oclk(l)
output clock frequency
lower limit oscillator
CLKSEL = 1
CLKSEL = 0
CLKSEL = 1
CLKSEL = 0
2
(8)
4
(8)
12.42
(7)
18.63
(7)
8.06
(7)
12.09
(7)
26
(8)
37
(8)
MHz
MHz
MHz
MHz
f
oclk(u)
output clock frequency
upper limit oscillator
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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