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參數(shù)資料
| 型號： | TDA1315H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital audio input/output circuit DAIO |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 411K |
| 代理商： | TDA1315H |
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1995 Jul 17
14
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Stand-alone mode
In this mode, the TDA1315H is automatically configured as
a receiver. The configuration, i.e., the mode of operation of
the device, is determined by pins CTRLMODE, IECSEL,
IECOEN, CLKSEL, I
2
SSEL and I
2
SOEN. Because all of
the pins have internal pull-up resistors, the default
configuration can be changed by pulling a pin LOW.
The output signals listed below are provided from the
channel status. However, all of them are switched off when
the PLL is not locked. This includes the situation where no
IEC input signal is available:
Sample frequency is 32 kHz (pin FS32)
Sample frequency is 44.1 kHz (pin FS44)
Sample frequency is 48 kHz (pin FS48)
Copyright status bit (pin COPY)
Pre-emphasis bit (pin DEEM).
As there will be no output signals from the channel status
in the event that non-consumer IEC signals are received,
the I
2
S-bus output will still output data in 24 bits format. An
LED can be connected to pin CHMODE to provide an
indication of such a situation.
Host mode
In this mode, the exchange of data and control information
between the TDA1315H and a microcontroller is via a
serial hardware interface, which comprises the following
pins:
LDATA to microcontroller interface data line.
LCLK to microcontroller interface clock line.
LMODE to microcontroller interface mode line.
LADDR to microcontroller interface address switch.
Two different modes of operation can be distinguished:
1.
Addressing mode.
2.
Data transfer mode.
The addressing mode is used to select a device for
subsequent data transfer and to define the direction of that
transfer as well as the source or destination registers. The
addressing mode is characterized by LMODE being LOW
and a burst of 8 clock pulses at LCLK, accompanied by
8 data bits. The fundamental timing is illustrated in Fig.6.
Data bits 0 to 1 indicate the type of subsequent data
transfer as given in Table 7. The direction of the channel
status and user data transfers depends on the
transmit/receive mode.
Data bits 2 to 7 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
TDA1315H is 000001 (LADDR = 0) or 000010
(LADDR = 1). Should the TDA1315H receive a different
address, it will immediately 3-state the LDATA pin and
deselect its microcontroller interface logic. A dummy
address of 000000 is defined for the deselection of all
devices that are connected to the serial microcontroller
bus.
Fig.3 User data handshake.
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