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參數(shù)資料
| 型號： | TDA1315H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital audio input/output circuit DAIO |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 411K |
| 代理商： | TDA1315H |
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1995 Jul 17
16
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Table 7
Selection of data exchange
In the data transfer mode, the microcontroller exchanges data with the TDA1315H after it has addressed the device and
defined the type of data for that exchange. The selection remains active until the TDA1315H receives a new type of data
or is deselected. The fundamental timing of data transfers is illustrated in Fig.7, where LDATA denotes the data from the
TDA1315H to the microcontroller (LDATA read). The timing for the opposite direction is essentially the same as in the
addressing mode (LDATA write).
BIT 1
BIT 0
TRANSFER
DIRECTION
0
0
1
1
0
1
0
1
channel status
user data
control
status
input/output
input/output
input
output
Fig.7 Data transfer mode timing.
All transfers are bytewise, i.e. they are based on groups of
8 bits. Data will be stored in the TDA1315H after the eighth
bit of each byte has been received. It is possible to read
only the first byte of the channel status and of the
TDA1315H status register.
A multi-byte transfer is illustrated in Fig.8. As some other
devices, which are expected to connect to the same
microcontroller bus lines, require an indication of when
8 bits have been transferred, a so-called halt mode has
been defined. It is characterized by the following
conditions: LMODE = LOW, LDATA = 3-state and
LCLK = HIGH. The TDA1315H does not need this mode to
distinguish one byte from the next, however, it will not
make any difference when this occurs. When not used,
there is no need to increase the time between the last
LCLK pulse of a byte and the first LCLK pulse of the next
byte.
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