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參數(shù)資料
| 型號： | T7693 |
| 廠商： | Lineage Power |
| 英文描述： | 3.3 V T1/E1 Quad Line Interface( 3.3 V T1/E四線接口) |
| 中文描述： | 四3.3伏的T1/E1線路接口（3.3伏T1 /電子四線接口） |
| 文件頁數(shù)： | 8/42頁 |
| 文件大小： | 726K |
| 代理商： | T7693 |
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T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
6
Lucent Technologies Inc.
11
GND
D
1
P
Ground Reference for Digital Circuitry
.
41
GND
D
2
61
GND
D
3
91
GND
D
4
12
V
DDD
1
P
Power Supply for Digital Circuitry
. The T7690 device requires a 5 V
±
5%
power supply on these pins. The T7693 device requires a 3.3 V
±
5% power
supply on these pins.
40
V
DDD
2
62
V
DDD
3
90
V
DDD
4
13
RND1/BPV1
O
Receive Negative Data.
When in dual-rail (DUAL = 1: register 5, bit 4)
clock recovery mode (CDR = 1: register 5, bit 0), this signal is the receive
negative NRZ output data to the terminal equipment. When in data slicing
mode (CDR = 0), this signal is the raw sliced negative output data of the
front end.
Bipolar Violation.
When in single-rail (DUAL = 0: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), and CODE = 1 (register 5,
bit 3), this signal is asserted high to indicate the occurrence of a code viola-
tion in the receive data stream. If CODE = 0, this signal is asserted to indi-
cate the occurrence of a bipolar violation in the receive data system.
39
RND2/BPV2
63
RND3/BPV3
89
RND4/BPV4
14
RPD1/
RDATA1
O
Receive Positive Data.
When in dual-rail (DUAL = 1: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), this signal is the receive posi-
tive NRZ output data to the terminal equipment. When in data slicing mode
(CDR = 0), this signal is the raw sliced positive output data of the front end.
Receive Data.
When in single-rail (DUAL = 0: register 5, bit 4) clock recov-
ery mode (CDR = 1: register 5, bit 0), this signal is the receive NRZ output
data.
38
RPD2/
RDATA2
64
RPD3/
RDATA3
88
RPD4/
RDATA4
15
RCLK1/
ALOS1
O
Receive Clock.
In clock recovery mode (CDR = 1: register 5, bit 0), this
signal is the receive clock for the terminal equipment. The duty cycle of
RCLK is 50%
±
5%.
Analog Loss of Signal.
In data slicing mode (CDR = 0: register 5, bit 0),
this signal is asserted high to indicate low-amplitude receive data at the
RTIP/RRING inputs.
37
RCLK2/
ALOS2
65
RCLK3/
ALOS3
87
RCLK4/
ALOS4
16
TND1
I
Transmit Negative Data.
Transmit negative NRZ input data from the termi-
nal equipment.
36
TND2
66
TND3
86
TND4
Table 1. Pin Descriptions
(continued)
Pin
Symbol
Type
*
Name/Description
* P = power, I = input, O = output, and I
u
= input with internal pull-up.
Pin Information
(continued)
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