參數(shù)資料
型號(hào): T7693
廠商: Lineage Power
英文描述: 3.3 V T1/E1 Quad Line Interface( 3.3 V T1/E四線接口)
中文描述: 四3.3伏的T1/E1線路接口(3.3伏T1 /電子四線接口)
文件頁(yè)數(shù): 26/42頁(yè)
文件大?。?/td> 726K
代理商: T7693
T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
24
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
Notes:
A numerical suffix appended to the bit name identifies the channel number.
Bits shown in parentheses indicate the state forced during a reset condition.
All registers must be configured by the user before the device can operate as required for the particular application.
Register 10 and register 11
must
be written to 0 after powerup of the device.
Registers 12—15 are reserved and should not be written. If they are written they must always be written with 0s.
Table 15. Register Set
Designation
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Alarm Registers (Read Only)
0
0000
LOTC2
TDM2
DLOS2
ALOS2
LOTC1
TDM1
DLOS1
ALOS1
1
0001
LOTC4
TDM4
DLOS4
ALOS4
LOTC3
TDM3
DLOS3
ALOS3
Alarm Mask Registers (Read/Write)
2
0010
MLOTC2
MTDM2
MDLOS2
MALOS2
MLOTC1
MTDM1
MDLOS1
MALOS1
3
0011
MLOTC4
MTDM4
MDLOS4
MALOS4
MLOTC3
MTDM3
MDLOS3
MALOS3
Global Control Registers (Read/Write)
4
0100
HIGHZ4 (1)
HIGHZ3 (1)
HIGHZ2 (1) HIGHZ1 (1)
ICTMODE (0)
LOSSTD
SWRESET
GMASK (1)
5
0101
LOSSD
ACM
ALM
DUAL
CODE
JAT
JAR
CDR
Channel Configuration Registers (Read/Write)
6
0110
EQA1
EQB1
EQC1
LOOPA1
LOOPB1
TBS1
MASK1
PWRDN1
7
0111
EQA2
EQB2
EQC2
LOOPA2
LOOPB2
TBS2
MASK2
PWRDN2
8
1000
EQA3
EQB3
EQC3
LOOPA3
LOOPB3
TBS3
MASK3
PWRDN3
9
1001
EQA4
EQB4
EQC4
LOOPA4
LOOPB4
TBS4
MASK4
PWRDN4
10
1010
0
0
0
0
0
0
0
0
11
1011
0
0
0
0
0
0
0
0
12—15
1100—1111
RESERVED
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