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Table of Contents
Contents
Page
Contents
Page
Lucent Technologies Inc.
T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
Features .................................................................... 1
Applications ............................................................... 1
Description ................................................................. 1
Block Diagram ........................................................... 3
Pin Information .......................................................... 4
System Interface Pin Options ................................ 9
Receiver .................................................................. 10
Data Recovery ..................................................... 10
Jitter ..................................................................... 10
Receiver Configuration Modes ............................ 10
Clock/Data Recovery Mode (CDR) ................... 10
Zero Substitution Decoding (CODE) ................. 10
Alternate Logic Mode (ALM) ............................. 10
Alternate Clock Mode (ACM) ............................ 11
Loss Shutdown (LOSSD) .................................. 11
Receiver Alarms .................................................. 11
Analog Loss of Signal (ALOS) Alarm ................ 11
Digital Loss of Signal (DLOS) Alarm ................. 11
Bipolar Violation (BPV) Alarm ........................... 11
DS1 Receiver Specifications ............................... 12
CEPT Receiver Specifications ............................. 13
Transmitter .............................................................. 14
Output Pulse Generation ..................................... 14
Jitter ..................................................................... 14
Transmitter Configuration Modes ........................ 15
Zero Substitution Encoding/Decoding
(CODE) ............................................................. 15
All Ones (AIS, Blue Signal) Generator (TBS) ... 15
Transmitter Alarms .............................................. 15
Loss of Transmit Clock (LOTC) Alarm .............. 15
Transmit Driver Monitor (TDM) Alarm ............... 15
DS1 Transmitter Pulse Template and
Specifications ...................................................... 16
CEPT Transmitter Pulse Template and
Specifications ...................................................... 17
Jitter Attenuator ....................................................... 18
Data Delay ........................................................... 18
Generated (Intrinsic) Jitter ................................... 18
Jitter Transfer Function ........................................ 18
Jitter Tolerance .................................................... 18
Jitter Attenuator Enable ....................................... 18
Jitter Attenuator Receive Path Enable (JAR) .... 19
Jitter Attenuator Transmit Path Enable (JAT) ... 19
Loopbacks ...............................................................19
Full Local Loopback (FLLOOP) ...........................19
Remote Loopback (RLOOP) ................................19
Digital Local Loopback (DLLOOP) .......................19
Other Features ........................................................20
Powerdown (PWRDN) .........................................20
RESET (RESET, SWRESET) ..............................20
Loss of XCLK Reference Clock (LOXC) ..............20
In-Circuit Testing and Driver 3-State (ICT) ..........20
Microprocessor Interface .........................................21
Overview ..............................................................21
Microprocessor Configuration Modes ..................21
Microprocessor Interface Pinout Definitions ........22
Microprocessor Clock (MPCLK) Specifications ...23
Internal Chip Select Function ...............................23
Microprocessor Interface Register
Architecture ..........................................................23
Alarm Register Overview (0000, 0001) .............25
Alarm Mask Register Overview (0010, 0011) ...25
Global Control Register Overview
(0100, 0101) ......................................................26
Channel Configuration Register Overview
(0110—1001) ....................................................27
Other Registers .................................................27
I/O Timing ............................................................28
XCLK Reference Clock ............................................33
Power Supply Bypassing .........................................33
T7690 External Line Termination Circuitry ...............34
T7693 External Line Termination Circuitry ..............35
Absolute Maximum Ratings .....................................36
Handling Precautions ..............................................36
Operating Conditions ...............................................36
Timing Characteristics .............................................37
Outline Diagram .......................................................39
100-Pin BQFP ......................................................39
Ordering Information ................................................39
DS98-233TIC Replaces DS97-098TIC
to Include the Following Updates .............................40