參數(shù)資料
型號(hào): T7289A
廠商: Lineage Power
英文描述: DS1 Line Interface(DS1 線接口)
中文描述: DS1的線路接口(DS1的線接口)
文件頁(yè)數(shù): 8/18頁(yè)
文件大?。?/td> 285K
代理商: T7289A
Data Sheet
January 1998
T7289A DS1 Line Interface
8
Lucent Technologies Inc.
Receive Converter
(continued)
Two methods of loss-of-signal detection are used in
this chip. The analog signal detector shown in Figure 5
uses the output of the receiver peak detector to deter-
mine if a signal is present at T1 and R1. If the input
amplitude drops below approximately 0.5 V, the analog
detector output becomes active. Hysteresis (250 mV) is
provided in the analog detector to eliminate
LOS
chat-
tering. In addition, the digital signal detector counts 0s
in the recovered data. If more than 128 consecutive 0s
occur, the digital signal detector becomes active. In
normal operation, the detector outputs are ORed
together to form
LOS
; however, in loopback 1, only the
digital signal detector is used to monitor the looped sig-
nal. Table 3 describes the operation of the shutdown,
LOS
, and
LOC
functions in normal operation and in
loopback 1.
The PLL is designed to accommodate large amounts of
input jitter with high power supply rejection for opera-
tion in noisy environments. Low jitter sensitivity to
power supply noise allows compact line-card layouts
that employ many line interfaces on one board. The
minimum input jitter tolerance, as specified in AT&T
Publication 43802, and the measured T7289A device
jitter tolerance are shown for the DS1 rate in Figure 6.
The data shown is typical for measurement to a BER of
10
–6
. Subtracting approximately 0.02 U.I. from the
given data yields the jitter accommodation for error-free
operation. Receiver specifications are shown in
Table 8.
Table 3. Shutdown,
LOS
, and
LOC
Truth Table
x = don't care.
Inputs
Input Signal
at T1, R1
Active
No Signal
Active
No Signal
Outputs
LP1
SD
ALMT
Loopback 1
Signal
x
x
x
x
Active
No Signal
Active
No Signal
x
LOS
LOC
Receive Side
Active LOS
Detectors
Analog and digital
Analog and digital
Analog and digital
Analog and digital
Digital only
Digital only
Digital only
Digital only
x
1
1
1
1
0
0
0
0
x
0
0
1
1
0
0
1
1
x
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
0
Normal
Free-running VCO
Normal
No output
Normal loopback
Free-running VCO
Normal loopback
No output
Unaffected
x
x
x
x
x
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