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參數(shù)資料
| 型號(hào)： | T7289A |
| 廠商： | Lineage Power |
| 英文描述： | DS1 Line Interface(DS1 線接口) |
| 中文描述： | DS1的線路接口（DS1的線接口） |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 285K |
| 代理商： | T7289A |
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Data Sheet
January 1998
T7289A DS1 Line Interface
7
Lucent Technologies Inc.
Transmit Converter
(continued)
Figure 5. T7289A Analog Block Diagram
5-4352(C)
EC1
ANALOG
SIGNAL
DETECTOR
RECEIVER
ANALOG
INPUT
M
U
X
PDATA
NDATA
T1
R1
TRANSMIT
OUTPUT
DRIVERS
D/A
SELECTABLE
PULSE
EQUALIZATION
T2
R2
CLOCK
MULTIPLIER
TIMING
SIGNALS
4
TCLK
TN DATA
TP DATA
DATA/CLOCK
RECOVERY
RPDATA
RNDATA
RCLK
DIGITAL
SIGNAL
DETECTOR
LOS
SD
RDATA/RPDATA
BPV/RNDATA
RCLK
TRANSMIT
AND
RECEIVE
LOGIC
TDATA/TPDATA
BZSC/TNDATA
TCLK
LP1
DUAL
EC2
EC3
Receive Converter
The receive converter accepts bipolar input signals
(T1, R1), coupled through a receive transformer, from
the cross connect over a maximum of 655 ft. of 22-
gauge PIC (ABAM) cable. The received signal is recti-
fied while the amplitude and rise time are restored.
These input signals are peak-detected and sliced by
the receiver front end, producing the digital signals
PDATA and NDATA (Figure 5). The timing is extracted
by means of phase-locked loop (PLL) circuitry that
locks an internal, free-running, current-controlled oscil-
lator (ICO) to the 1.544 MHz (DS1 signal) component.
The PLL employs a 3-state phase detector and a low-
voltage/temperature coefficient ICO. The ICO free-
running frequency is trimmed to within
±
2.5% of the
data rate at wafer probe, with V
DD
= 5.0 V and
T
A
= 25
°
C. For all operating conditions (see Operating
Conditions section), the free-running oscillator fre-
quency deviates from the data rate by less than
±
6%,
alleviating the problem of harmonic lock.
For robust operation, the PLL is augmented with a
frequency-acquisition capability. The frequency acquisi-
tion circuitry is intended to guarantee proper phase-
locking during start-up conditions, such as powerup or
data activation. Once the T7289A device is phase-
locked to data, the frequency-acquisition mode will
not
be activated.
A continuous (i.e., ungapped, unswitched) 1.544 MHz
reference clock must be present at TCLK to enable the
frequency-acquisition circuitry. However, the receive
PLL will operate even in the absence of TCLK.
Because the clock output of the receive converter is
derived from the ICO, a free-running clock can be
present at the output of the receive converter without
data being present at the input. A shutdown pin (SD) is
provided to block this clock, if desired, to eliminate the
free-running clock upon loss of the input signal.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| T7289A-EL | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DS1 LINE INTERFACE |
| T7289A-EL4 | 制造商:Legerity 功能描述:IC,PCM TRANSCEIVER,SINGLE,T-1(DS1),CMOS,SOJ,28PIN,PLASTIC |
| T7289A-PL | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DS1 LINE INTERFACE |
| T7290 | 制造商:TE Connectivity 功能描述: |
| T-7290 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:T7290 DS1/T1/CEPT Line Interface |
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