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參數(shù)資料
| 型號： | T7289A |
| 廠商： | Lineage Power |
| 英文描述： | DS1 Line Interface(DS1 線接口) |
| 中文描述： | DS1的線路接口（DS1的線接口） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 285K |
| 代理商： | T7289A |
Data Sheet
January 1998
T7289A DS1 Line Interface
6
Lucent Technologies Inc.
Transmit Converter
The line-interface transmission format is return-to-zero,
bipolar alternate mark inversion (AMI), requiring trans-
mission and sensing of alternately positive and nega-
tive pulses. During single-rail operation, the transmit
converter accepts unipolar data at TDATA and converts
the signal to a balanced bipolar data signal. Binary 1s
in the TDATA data stream become pulses of alternating
polarity transmitted between the two output rails, T2
and R2. For dual-rail operation, a binary 1 on TPDATA
results in the transmission of a positive pulse between
T2 and R2, and a binary 1 on TNDATA results in a neg-
ative pulse. Binary 0s are transmitted as null pulses. All
necessary transmit pulse shaping is done on-chip,
eliminating the need for external shaping networks.
This is done by shaping the pulses at the bipolar output
(T2, R2) according to the selected equalizer control
(EC1—EC3) inputs (see Table 2).
The output pulse waveform consists of four distinct lev-
els: overshoot, pulse, backswing, and tail. They are
produced by a high-speed D/A converter and are
driven onto the line by using low-impedance output
buffers. There are five different pulse shapes, corre-
sponding to 133-ft. increments of cable, that are
obtained by setting the appropriate equalizer control
inputs. The positive and negative pulses meet the
amplitude, rise and fall time, overshoot, undershoot,
template, and power requirements for the office DSX
cross connect as given in Compatibility Bulletin 119
(CB119). A typical DS1 output waveform at the DSX
relative to the CB119 template is shown in Figure 4.
The analog circuitry is shown in Figure 5.
The clock multiplier shown in Figure 5 produces the
high-speed timing waveforms needed by the D/A con-
verter. The clock multiplier also eliminates the need for
the tightly controlled transmit clock duty cycle usually
required in discrete implementations. Transmitter spec-
ifications are given in Table 7.
Figure 4. Typical T7289A Output Waveform at DSX
N
1.0
0.5
0
–0.5
0
250
500
750
1000
1250
TIME (ns)
CB119
TEMPLATE
T7289A
OUTPUT
PULSE
SHAPE
5-4351(C)
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