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參數(shù)資料
| 型號： | T7289A |
| 廠商： | Lineage Power |
| 英文描述： | DS1 Line Interface(DS1 線接口) |
| 中文描述： | DS1的線路接口（DS1的線接口） |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 285K |
| 代理商： | T7289A |
Data Sheet
January 1998
T7289A DS1 Line Interface
3
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
This table refers to a cleared pin as low (0) and a set pin as high (1).
* I = input, O = output, Iu = input with pull-up, Id = input with pull-down, Ou = output with pull-up.
See Table 2.
Pin
1
Symbol
LOS
Type*
O
Name/Function
This pin is cleared upon loss of the data
u
Loss of Signal (Active-Low).
signal at the receiver inputs.
Loss of Clock (Active-Low).
LOS
= 0, indicating that a loss of clock has occurred. When
transitions occur on the RCLK and
present at BCLK for this function to operate properly.
B8ZS Enable/Transmit Data Negative Rail.
insert a B8ZS substitution code on the transmit side and to remove the
substitution code on the receive side. If dual = 1, this pin is used as the
transmit data negative rail.
Bipolar Violation/Receive Data Negative Rail.
upon detection of a bipolar violation on the receive-side input after the
removal of the B8ZS substitution code that contains legal violations. If
dual = 1, this pin is used as the receive data negative rail.
Receive Clock.
Output receive clock signal to the terminal equipment.
Receive Data (Active-Low)/Receive Data Positive Rail.
this pin is used as 1.544 Mbits/s inverted unipolar output data with a
100% duty cycle. If dual = 1, this pin is used as the transmit data positive
rail.
Transmit Clock.
DS1 input clock signal (1.544 MHz
Transmit Data/Transmit Data Positive Rail.
as 1.544 Mbits/s unipolar input data. If dual = 1, this pin is used as the
transmit data positive rail.
Loopback 1 Enable (Active-Low).
This pin is cleared for a full local
loopback (transmit converter output to receive converter input). Most of
the transmit and receive analog circuitry is exercised in this loopback.
Loopback 2 Enable (Active-Low).
This pin is cleared for a remote loop-
back (DSX to DSX). In loopback 2, a high on TBC (pin 14) inserts the
blue signal on the transmit side.
Loopback 3 Enable (Active-Low).
This pin is cleared for a digital local
loopback. Only the transmit and receive digital sections are exercised in
this loopback.
Alarm Test Enable (Active-Low).
This pin is cleared, forcing
LOC
= 0, and BPV = 1 for testing without affecting data transmission.
Receive Blue Control.
This pin is set to insert the blue signal on the
receive side. During single-rail mode,
mode, RPDATA and RNDATA toggle at half the blue clock rate. Blue
clock must be present.
2
LOC
O
u
This pin is cleared when SD = 1 and
LOC
= 0, no
RDATA
outputs. A valid clock must be
3
BZSC/TNDATA
I
d
If dual = 0, this pin is set to
4
BPV/RNDATA
O
If dual = 0, this pin is set
5
6
RCLK
/RPDATA
O
O
RDATA
If dual = 0,
7
8
TCLK
I
I
±
130 ppm).
TDATA/TPDATA
If dual = 0, this pin is used
9
LP1
I
u
10
LP2
I
u
11
LP3
I
u
12
ALMT
I
u
LOS
= 0,
13
RBC
I
d
RDATA
is cleared. During dual-rail
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| T7289A-EL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DS1 LINE INTERFACE |
| T7289A-EL4 | 制造商:Legerity 功能描述:IC,PCM TRANSCEIVER,SINGLE,T-1(DS1),CMOS,SOJ,28PIN,PLASTIC |
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