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參數(shù)資料
| 型號： | T7289A |
| 廠商： | Lineage Power |
| 英文描述： | DS1 Line Interface(DS1 線接口) |
| 中文描述： | DS1的線路接口（DS1的線接口） |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 285K |
| 代理商： | T7289A |
Data Sheet
January 1998
T7289A DS1 Line Interface
13
Lucent Technologies Inc.
Electrical Characteristics
(continued)
Operating Conditions
(continued)
Table 8. Receiver Specifications
* Minimum sensitivity (maximum cable loss limit) occurs when the frequency of Vac is near the clock rate.
Timing Characteristics
All duty cycle and timing relationships are referenced to a TTL 1.4 V threshold level.
Loss-of-Clock Indication Timing
The clock must be absent 5.18
μ
s to guarantee a loss-of-clock indication. However, it is possible to produce a loss-
of-clock indication if the clock is absent for 2.59
μ
s depending on the timing relationship of the interruption with
respect to the timing cycle.
The returning clock must be present 5.18
μ
s to guarantee a normal condition on the loss-of-clock pin (
LOC
). How-
ever, the loss-of-clock indication can return to normal immediately, depending on the timing relationship of the sig-
nal return with respect to the timing cycle.
Table 9. System Interface
* A tolerance of
±
130 ppm.
Parameter
Condition
—
Min
0.85
Typ
—
33
1.2
12
Max
—
Unit
Vp
Receiver Sensitivity (at input of device)
PLL:
3 dB Bandwidth
Peaking
Allowed Cable Loss* at BER = 10
–9
1/8 input
1/8 input
V
DD
= 5.0 V;
Vac on V
DD
= 0.5 Vpp,
from dc to 4 MHz
Maximum number of
consecutive 0s = 15
—
—
—
Each Input to Ground
—
—
—
—
2.0
9
kHz
dB
dB
Input Density (1s)
12.5
—
—
%
ICO Free-running Frequency Error
Input Transformer Turns Ratio
Input Termination
Input Resistance, R1 or T1
—
1:1.9
—
0.9
—
1:2.0
100
—
±
6
1:2.1
—
3.0
%
—
k
Symbol
tTCLTCL
tTCHTCL
tTDVTCL
tTCLTDV
tr
tf
tRCHRDV
tRDVRCH
tRCLRDV
Description
Min
*
40
50
40
—
—
227
187
—
Typ
647.7
50
—
—
—
—
—
—
—
Max
*
60
—
—
40
40
—
—
40
Unit
ns
%
ns
ns
ns
ns
ns
ns
ns
TCLK Clock Period
TCLK Duty Cycle
Data Setup Time, TDATA to TCLCK
Data Hold Time, TCLK to TDATA
Clock Rise Time (10%—90%)
Clock Fall Time (10%—90%)
Data Hold Time, RCLK to
RDATA
, BPV
Data Setup Time,
RDATA
, BPV to RCLK
Propagation Delay, RCLK to
RDATA
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