參數(shù)資料
型號(hào)： T7256
廠商： Lineage Power
英文描述： ISDN Transceiver(ISDN收發(fā)器)
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)收發(fā)器（綜合業(yè)務(wù)數(shù)字網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 697K
代理商： T7256
SCNT1 Family Reference Design Board
Hardware User’s Manual
Manual
May 1996
12
Lucent Technologies Inc.
Description
(continued)
Jumper Options
The SCNT1-RDB contains several options that are
jumper-selectable. All of the jumpers are oriented on
the board such that, when looking at the front of the
board with the silkscreen lettering positioned as it
would be read, pin 1 of the jumper is always the left-
most pin. Note that the reference designators JMP4
and JMP6 are not used on the board. These positions
are skipped.
Jumpers JMP5 and JMP11 are reserved for future use.
The default is for these jumpers to be installed. To
ensure this, they have a hardwired shorting trace
between the pins on the bottom side of the board. If
these jumpers are defined for use in the future, the
trace can easily be cut so that the jumpers can be open
if desired. These jumpers are pictured on the sche-
matic as jumpers with a bold line between the pin con-
nections, and they are reserved for future use.
On the two 3-position jumpers (JMP1 and JMP3), the
default jumper position is indicated on the schematic by
a curved line between the two pins on which the jumper
should be installed. Table 5 lists all of the jumpers on
the SCNT1 board and the functions they control.
* 3-position jumpers.
Table 5. Jumper Options
Jumper
JMP1*
Description
Default
Controls the state of the T7237/56 ACTSEL bit in register GR2 when
the RESET state is exited. If pins 1 and 2 are shunted, ACTSEL = 1
upon exiting RESET. If pins 2 and 3 are shunted, ACTSEL = 0 upon
exiting RESET.
Enables the power-on reset (POR) circuit. When installed, this jumper
enables the POR circuit to provide a reset signal to pin 43 (RESET) of
the T7234/37/56 when power is initially applied. When not installed,
RESET is pulled up through a 5.1K resistor and can be controlled exter-
nally via the general-purpose interface or the FADS adapter interface.
Controls whether the T7256 S/T-interface operates in adaptive timing
mode (pins 1 and 2 shunted) or fixed timing mode (pins 2 and 3
shunted). Note that when the TDM highway is enabled, this jumper is
not applicable because pin 7 of the T7237/56 becomes TDMDI and the
timing mode is controlled by the FT bit (register GR2 bit 5).
There is no JMP4 location on the board.
Reserved for future use.
There is no JMP6 location on the board.
This jumper and JMP8 allow for a 50
termination option on the S/T-
interface of the NT1 instead of the standard 100
termination. This is
useful in configurations where none of the TEs have terminating resis-
tors. Referring to Figure 2/I.430 in the ITU-TI.430 standard, installing
this jumper has the effect of combining the two termination resistors
(TR) at the NT1.
See JMP7.
Jumpers JMP9 and JMP10 are provided to allow the +5VD and +5VA
sections to be individually isolated. This can be useful for chip power
measurements or off-nominal voltage testing. In this case, the +5VD
and/or +5VA power would be supplied by connecting an external supply
to pin 2 of JMP9 and/or JMP10.
See JMP9.
Reserved for future use.
Pins 1 and 2
shunted
JMP2
Installed
JMP3*
Pins 1 and 2
shunted
JMP4
JMP5
JMP6
JMP7
NA
Hardwired
NA
Not installed
JMP8
JMP9
Not installed
Installed
JMP10
JMP11
Installed
Hardwired
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