參數(shù)資料
型號(hào)： T7256
廠商： Lineage Power
英文描述： ISDN Transceiver(ISDN收發(fā)器)
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)收發(fā)器（綜合業(yè)務(wù)數(shù)字網(wǎng)收發(fā)器）
文件頁數(shù)： 13/36頁
文件大?。?/td> 697K
代理商： T7256
Lucent Technologies Inc.
11
Manual
May 1996
SCNT1 Family Reference Design Board
Hardware User’s Manual
Description
(continued)
* See T7256 Single-Chip NT1 (SCNT1) TransceiverData Sheet pin
descriptions for details.
FADS Adapter Interface
. An interface to a Lucent
Technologies FADS Adapter Card is provided through
J4, the FADS Adapter Interface. The FADS Adapter
Card connects the SCNT1-RDB to the connectors on
the MotorolaMC68302 Family Application Development
System (68302FADS) so that the microprocessor port
on the SCNT1-RDB can be controlled by the serial con-
trol port (SCP) on the MC68302 and the TDM highway
can connect to the serial communication controller
(SCC) ports on the MC68302. This facilitates develop-
ment of ISDN applications based on the Motorola
MC68302. This interface is useful for controlling the
SCNT1-RDB when it is used in NT1+ or TA mode. Table
4 defines the MC68302 signals that are available at the
general-purpose interface when the MC68302 FADS
board is connected to the SCNT1-RDB via the FADS
Adapter Card. For the MC68302 pins that have multiple
functions, the signal names shown in
boldface
are
those that are designated for use with the SCNT1-RDB.
When using the MC68302 FADS board (connected via
the FADS Adapter Card), a portion of the prototype
EPLD is required in order to provide the necessary glue
for interfacing to the SCCs of the MC68302 (note that
this glue circuitry is not required when interfacing to the
MotorolaMC68360). The AlteraMaxplus+ II design files
for an EPM7032 device that contains the necessary
interface circuitry are listed in Appendix B. This design
is the same as the one shown in the T7256/MC68302
Interface Circuit figure depicted in the T7256 Single-
Chip NT1 (SCNT1) TransceiverData Sheet, where the
circuit operation is explained in more detai
l.
Table 3. General-Purpose Interface Connector Signals
Pin No.
Signal
Name
G
NDD
+5V
G
NDD
NC
SCK
CKOUT
INT\
SDO
SDI
TDMCLK
TDMDO
TDMDI
SYN8K
ILOSS\
RESET\
HIGHZ\
Signal Description
*
1
2
3
4
5
6
7
8
9
Digital ground
Digital +5 Vdc
Digital ground
Not connected
Serial interface clock
Programmable clock output
Serial interface interrupt
Serial interface data output
Serial interface data input
TDM clock
TDM data out
TDM data in
Synchronous 8 kHz clock
Insertion loss test control
Reset
High-impedance control
10
11
12
13
14
15
16
Table 4. FADS Adapter Interface Connector Signals
Pin
No.
1
2
3
SCNT1_RDB
Signal Name
G
NDD
+5V
INT\
MC68302
Signal Name
G
ND
V
DD
IPL1*/
IRQ6*
Comment
Ground
Power
Output from
SCNT1 Family
pin 11
Input to SCNT1
Family pin 15
Output from
SCNT1 Family
pin 14
Input to SCNT1
Family pin 12
Output from
EPLD pin 7
Output from
SCNT1 Family
pin 8
Input to SCNT1
Family pin 7
Output from
EPLD pin 8
Output from
EPLD pin 9
Input to EPLD
pin 43
Input to EPLD
pin 1
I/O to EPLD
pin 16
I/O to EPLD
pin 13
I/O to EPLD
pin 14
Output from
EPLD pin 41
Not connected
Not connected
4
SCK
CD3*/
SPCLK
5
SDO
CTS3*/
SPRXD
6
SDI
RTS3*/
SPTXD
7
L1CLK
RCLK1/
L1CLK
8
TDMDO
RXD1/
L1RXD
9
TDMDI
TXD1/
L1TXD
10
L1SY0
TCLK1/
L1SY0
/
SDS1
CD1*/
L1SY1
11
L1SY1
12
7BIT_B1
RXD2/
PA0
13
7BIT_B2
TXD2/
PA1
14
IO_0
RCLK2/
PA2
15
IO_1
TCLK2/
PA3
16
IO_2
CTS2*/
PA4
17
IO_Q1
IPL0*/
IRQ1*
18
19
20
21
22
23
24
25
NC
NC
NC
NC
NC
NC
NC
RTS2*/
PA5
CD2*/
PA6
BRG2/SDS2/
PA7
Not connected
RXD3/
PA8
TXD3/
PA9
RCLK3/
PA10
TCLK3/
PA11
RESET*
Not connected
Not connected
Not connected
Not connected
Input to T7234/
37/ pin 43 via
JMP12
Not connected
Not connected
Not connected
Power
Ground
RESET\
26
27
28
29
30
NC
NC
NC
+5V
G
NDD
Spare
Spare
Spare
V
DD
G
ND
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