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參數(shù)資料
| 型號： | T7256 |
| 廠商： | Lineage Power |
| 英文描述： | ISDN Transceiver(ISDN收發(fā)器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)收發(fā)器（綜合業(yè)務(wù)數(shù)字網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 697K |
| 代理商： | T7256 |
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Lucent Technologies Inc.
9
Manual
May 1996
SCNT1 Family Reference Design Board
Hardware User’s Manual
Description
(continued)
Status LED
D1 is a green LED that is controlled by the STLED pin
of the SCNT1 Family and indicates the status of the
device (activating, out-of-sync, etc.). Table 30 and Fig-
ure 21 of the T7256 Single-Chip NT1 (SCNT1) Trans-
ceiverData Sheet detail the possible states of the
STLED pin and the meaning of each state.
POR Circuit
The power-on reset circuit consists of R4 and C2, and
it provides a reset signal to the SCNT1 Family when
power is first applied. A two-position jumper (JMP2) is
provided to allow disconnection of capacitor C2 from
the circuit so that there is no time constant on the
RESET\ signal. This is useful if RESET\ is being con-
trolled by external circuitry connected to the general-
purpose interface or FADS adapter interface. In the
stand-alone mode of operation, JMP2 should be
installed.
Power Status Leads
ANSI T1.601 Section 8.2.4 defines U-interface NT
power status bits ps1 and ps2. These bits are transmit-
ted across the U-interface via the U-maintenance chan-
nel. On the T7234/37/56 ICs, these bits are controlled
by pins 8 and 9 (PS2E and PS1E). When the TDM
highway on the T7256 or T7237 is used (NT1+ or TA
modes), the ps1/ps2 bits are controlled by internal reg-
isters that are written by an external microprocessor.
An NT1 typically has circuitry that monitors the status
of the power supply and sets ps1 and ps2 accordingly.
There is not power status monitoring circuitry on the
SCNT1-RDB. Instead, pull-ups R1 and R3 are provided
to force a default indication of primary and secondary
power good status. The general-purpose interface con-
nector brings out pins 8 and 9, V
CC
and GND, which
allows external power status monitoring circuitry to
monitor the power level and control the power status
pins. This allows for convenient testing of power status
circuits.
Fixed/Adaptive Timing Control
As detailed in the T7256 Single-Chip NT1 (SCNT1)
TransceiverData Sheet, pin 7 of the SCNT1 Family
controls whether the S/T-interface will use fixed or
adaptive timing recovery. When there is no connection
to pin 7, an internal 100K pull-up holds the pin high,
which causes the chip to default to adaptive timing
recovery. JMP3 is provided to change the timing recov-
ery mode to fixed timing by pulling pin 7 down through
a 10K resistor.
Figure 5 Circuits—S/T-Interface
The S/T-interface attaches to the board at RJ-45 con-
nector J2 (see Figure 4). This interface and its related
components are not required when using the T7234/
37/56. L1 is a high-frequency common-mode choke
used to minimize EMI. R24 and R25 are 100
termi-
nations required by ITU I.430 Section 8.4. Jumper-
selectable resistors R26 and R27 provide for a 50
termination option instead of the standard 100
termi-
nation. This is useful in configurations where none of
the TEs have terminating resistors. Dual transformer
T2 has a standard footprint that can accept ISDN trans-
formers from several vendors. On the device-side of the
S/T-interface transformer, D2—D10 and D12, as well as
VR3—VR4 provide overvoltage protection for the
device pins. R20—R23 provide current limiting for
cases where one or more of the protection diodes con-
ducts due to an overvoltage condition. Capacitor C18
provides suppression of common-mode noise that
might otherwise be introduced onto the receiver input
pins, effectively increasing the receiver's CMRR. Note
that the S/T transformer must have a center tap on the
device side in order to use this scheme. R16 and R17
in combination with R20 and R21, respectively, provide
the 121
of resistance required by the T7234/37/56 on
each transmitter output pin. R18 and R19 are the 10K,
10% resistors required on the receiver input pins.
Figure 6 Circuits
The following paragraphs discuss those circuits found
in Figure 6.
Board Powering Options
. The power for the SCNT1-
RDB is supplied through connector J5 when the board
is operated in stand-alone mode. Included with the
board is an Augateuro block connector that mates to
J5. This provides a simple way to connect an external
power supply. Power to the board may also be applied
through the general-purpose interface (J3) or the FADS
adapter interface (J4). When the MotorolaMC68302
FADS board is used, the default is for the FADS board
to provide power to the SCNT1-RDB. Regardless of the
location of the power source, board power is fused by
F2, a 1A fuse. The board power plane is divided into
four sections, as detailed in Table 2.
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