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參數(shù)資料
| 型號： | T7256 |
| 廠商： | Lineage Power |
| 英文描述： | ISDN Transceiver(ISDN收發(fā)器) |
| 中文描述： | 綜合業(yè)務數(shù)字網(wǎng)收發(fā)器（綜合業(yè)務數(shù)字網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 697K |
| 代理商： | T7256 |
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10
Lucent Technologies Inc.
SCNT1 Family Reference Design Board
Hardware User’s Manual
Manual
May 1996
Description
(continued)
Jumpers JMP9 and JMP10 are provided to allow the
+5VD and +5VA sections to be individually isolated.
This can be useful for chip power measurements or off-
nominal voltage testing. In this case, the +5VD and/or
+5VA power would be supplied by connecting an exter-
nal supply to pin 2 of JMP9 and/or JMP10.
Board Ground Planes
. The SCNT1-RDB has two
ground plane sections. One is a digital ground that con-
nects to the G
NDD
pins of the T7234/37/56 and to all
other board grounds except the G
NDA
pins of the
T7234/37/56. The other is an analog ground plane that
connects only to the V
DDA
pins of the T7234/37/56 and
to any related grounds on the analog section of the
chip. The board power/ground planes and signal layers
are shown in Appendix A.
Prototyping EPLD
. A socket is provided at location U4
for an Altera EPM7032 or EPM7064 44-pin PLCC
device. The EPLD can be used as an on-board digital
prototyping area to experiment with various NT1 sup-
port circuits that may be desired. Some of the more
commonly used signals are routed to pins of U4. Oth-
ers can be easily white-wired to the socket pins on the
bottom side of the board. Macrocell MC12 is tied to the
I/OE1n input so that on-chip circuitry can control the tri-
state function of the output macrocells.
If there is a requirement to drive the I/OE2n input with
an external signal, JMP11 is provided. JMP11 is a
jumper block footprint with a shorting trace on the
bottom side of the board so that the trace can be easily
cut. The external signal can then be connected to pin 2
of JMP11 with a white wire to drive the I/OE2n signal.
Normally, this signal is grounded (all input signals to
the EPLD must be tied high or low).
Five Port A pins and the IPL0* interrupt pin of the
MC68302 FADS board are routed to U4 (via pins 12—
17 of the FADS adapter interface) for potential use as
control, status, and interrupt leads. The signals are
pulled high through 10K resistors so that the input pins
to the EPLD that they drive are pulled high if those sig-
nals are not being driven by the FADS interface.
General-Purpose Interface
. A general-purpose inter-
face, J3, is provided on the board, allowing access to
the T7237/56 TDM highway signals, the serial micro-
processor interface signals, and control signals. Exter-
nal control circuits such as the Lucent Technologies
SPEC_V2 board can connect to this interface to allow
access to the SCNT1 Family microprocessor registers.
Table 3 defines the signals that are accessible at the
general-purpose interface.
Table 2. SCNT1-RDB Power Plane Sections
Section
Power In
Description
Power arriving on the board before
fuse F2.
Power for all board circuitry except
the T7234/37/56 digital and analog
power supplies.
Power for the V
DDD
pins of the
T7234/37/56.
Power for the V
DDA
pins of the
T7234/37/56.
+5V
+5VD
+5VA
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