參數資料
型號: T431616B-10S
廠商: TM Technology, Inc.
英文描述: 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述: 100萬× 16內存為512k × 16Bit的X 2Banks同步DRAM
文件頁數: 9/31頁
文件大小: 567K
代理商: T431616B-10S
TE
CH
tm
AC CHARACTERISTICS
(AC opterating conditions unless otherwise noted)
T431616B
Taiwan Memory Technology, Inc. reserves the right
P.9
to change products or specifications without notice.
Publication Date: JUL. 2001
Revision:A
-10
-20
Parameter
Symbol
Min
Max
Min
Max
Unit
Note
CAS Latency =
3
CAS Latency =
2
CAS Latency =
1
CAS Latency =
3
CAS Latency =
2
CAS Latency =
1
CAS Latency =
3
CAS Latency =
2
CAS Latency =
1
10
20
10
20
CLK cycle time
t
CC
20
1K
40
1K
ns
1
-
7
-
18
-
9
-
18
CLK to valid
Output delay
t
SAC
-
20
-
38
ns
1
2.5
-
2.5
-
2.5
-
2.5
-
Output data
hold time
t
OH
4
-
4
-
ns
2
CLK high pulse width
t
CH
t
CL
t
SS
t
SH
t
SLZ
3
-
8
-
ns
3
CLK low pulse width
3
-
8
-
ns
3
Input setup time
2.5
-
4
-
ns
3
Input hold time
1
-
2
-
ns
3
CLK to output in Low-Z
1
-
1
-
ns
2
CAS Latency =
3
CAS Latency =
2
CAS Latency =
1
-
7
2
14
-
9
2
14
CLK to output in
Hi-Z
t
SHZ
-
14
4
19
ns
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns,transient time compensation should be considered,
i.e.,[(tr+tf)/2-1]ns should be added to the parameter.
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