參數(shù)資料
型號(hào): T431616B-10S
廠商: TM Technology, Inc.
英文描述: 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述: 100萬(wàn)× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM
文件頁(yè)數(shù): 17/31頁(yè)
文件大小: 567K
代理商: T431616B-10S
TE
CH
tm
Read & Write Cycle at Same Bank @Burst Length = 4
T431616B
Taiwan Memory Technology, Inc. reserves the right
P.17
to change products or specifications without notice.
Publication Date: JUL. 2001
Revision:A
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
t
RC
D Q M
D Q
: D o n ' t c a r e
*Note1
t
RCD
*Note2
*Note4
*RAC
*Note3
*Note4
R a
C a 0
R b
C b 0
R b
R a
Q a 0
Q a 1
Q a 2
Q a 3
Q a 0
Q a 1
Q a 2
Q a 3
D b 0
D b 0
D b 1
D b 1
D b 2
D b 2
D b 3
D b 3
t
SAC
t
OH
t
OH
t
SAC
t
SHZ
t
SHZ
t
RDL
t
RDL
Row
Active (A-
Bank)
Read (A-
Bank)
Precharg
e (A-
Bank)
Row Active
(A-Bnak)
Write (A-
Bnak)
Precharge
(a-Bnak)
*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z(
t
SHZ
) after the clock.
3. Access time from Row active command.
t
CC
*(
t
RCD
+CAS latency-1)+
t
SAC
4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)Burst can’t end in Full Page Mode.
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