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IX-8
Index
state D0
2-60
state D1
2-60
state D2
2-61
state D3
2-61
power state (PWS[1:0])
4-17
prefetch
enable (PFEN)
4-69
flush
2-22
flush (PFF)
4-69
SCRIPTS instructions
2-21
pull-ups, internal, conditions
3-3
R
RAM, see also SCRIPTS
RAM
2-18
RBIAS
3-17
read
line
2-10
function
2-7
modify-write cycles
5-23
multiple
2-7
multiple with read line enabled
2-7
write instructions
5-21
write system memory from SCRIPTS
5-33
read/write
instructions
5-21
,
5-24
system memory from SCRIPTS
5-33
received
master abort (from master) (RMA)
4-5
target abort (from master) (RTA)
4-5
register
address
5-36
address - A[6:0]
5-22
registers
2-42
relative
5-19
relative addressing mode
5-17
,
5-28
remaining byte count (RBC)
4-104
REQ/
3-8
request
3-8
reselect
2-17
during reselection
2-38
instruction
5-14
reselected (RSL)
4-73
,
4-76
reserved
4-4
,
4-6
,
4-10
,
4-13
,
4-16
,
4-17
,
4-23
,
4-31
,
4-36
,
4-39
,
4-41
,
4-52
,
4-68
,
4-74
,
4-78
,
4-84
,
4-87
,
4-93
,
4-95
,
4-96
,
4-98
,
4-102
,
4-106
reserved command
2-5
reset
3-4
input
6-11
SCSI offset (ROF)
4-89
response ID one (RESPID1)
4-85
response ID zero (RESPID0)
4-85
return instruction
5-27
revision ID (RID)
4-7
ROM
flash and memory interface signals
3-14
pin
2-55
RST/
3-4
S
SACK
2-47
SACK+-
3-13
SACK/ status (ACK)
4-40
SACK2+-
3-13
SACs
2-19
SATN/ status (ATN)
4-40
SATNM+-
3-13
SBSY/ status (BSY)
4-40
SC_D+-
3-13
SC_D/ status (C_D)
4-40
SCLK
3-11
(SCLK)
4-87
quadrupler enable (QEN)
4-87
quadrupler select (QSEL)
4-88
SCNTL0
2-25
SCNTL1
2-24
,
2-25
SCNTL3
2-39
,
2-40
scratch
byte register (SBR)
4-69
register A (SCRATCHA)
4-65
register B (SCRATCHB)
4-99
registers C–R (SCRATCHC–SCRATCHR)
4-99
script fetch selector (SFS)
4-101
SCRIPTS
instruction
2-50
interrupt instruction received (SIR)
4-41
,
4-68
processor
2-17
internal RAM for instruction storage
2-18
performance
2-17
RAM
2-3
,
2-18
running (SRUN)
4-52
SCRIPTS (SCPTS)
4-81
SCSI
ATN condition - target mode (M/A)
4-72
bit mode change (SBMC)
4-78
bus control lines (SBCL)
4-39
bus data lines (SBDL)
4-97
bus interface
2-33
bus mode change (SBMC)
4-74
byte count (SBC)
4-105
C_D/ signal (C_D)
4-46
chip ID (SCID)
4-31
clock
3-11
control
3-13
control enable (SCE)
4-88
control one (SCNTL1)
4-24
control three (SCNTL3)
4-29
control two (SCNTL2)
4-27
control zero (SCNTL0)
4-21
data high impedance (ZSD)
4-60
destination ID (SDID)
4-36
disconnect unexpected (SDU)
4-27
encoded destination ID
5-19
FIFO test read (STR)
4-90
FIFO test write (STW)
4-92
first byte received (SFBR)
4-37
functional description
2-16
GPIO signals
3-10
gross error (SGE)
4-73
,
4-76
I_O/ signal (I/O)
4-46
input data latch (SIDL)
4-92
instructions
block move
5-5
I/O
5-12
read/write
5-21
interface signals
3-11
interrupt enable one (SIEN1)
4-74
interrupt enable zero (SIEN0)
4-72
interrupt pending (SIP)
4-50
interrupt status one (SIST1)
4-78