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參數(shù)資料
| 型號： | SYM53C180 |
| 廠商： | LSI Corporation |
| 英文描述： | Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴展器) |
| 中文描述： | 個Ultra3 SCSI總線擴展（Ultra2的SCSI總線擴展器） |
| 文件頁數(shù)： | 32/78頁 |
| 文件大?。?/td> | 1073K |
| 代理商： | SYM53C180 |
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2-14
Functional Descriptions
2.2 Internal Control Descriptions
This section provides information about self-calibration, delay line
structures, and busy filters.
2.2.1 Self-Calibration
The SYM53C180 contains internal logic that adjusts the internal timing
based on analyzing the time through a long asynchronous inverter logic
chain versus a synchronous counter. The timing functions use the
resulting self-calibration value to adjust to their nominal values based on
the performance of this circuit.
The SYM53C180 has 24 critical timing chains and each has its own
calibration circuit and stored calibration value. The counter logic is
replicated four times so four calibrations can occur in parallel. This allows
the 24 calibration values to be updated by six calibration cycles.
Self-calibration is triggered every 8.1 seconds to account for temperature
and voltage changes.
2.2.2 Delay Line Structures
Some fixed delay functions are required within the signal and control
interfaces from bus to bus. The SYM53C180 uses programmable delay
lines to implement delays. The incremental points in the chain are
selected by multiplexers. Self-calibration takes care of process,
temperature, and voltage effects.
2.2.2.1 Data Path
The data path through the SYM53C180 includes two levels of latches.
One latch is in the receiver and the input clock, REQ or ACK, generates
the hold. This level captures the data that may have minimal setup and
hold. A second latch occurs to hold the data in order to transmit optimal
signals on the isolated bus. This level provides maximum setup and hold
along with a regenerated clock. The data path also provides a timer for
each data bit that protects reception from a target bus for a nominal
30 ns after the driver is deasserted.
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