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參數(shù)資料
| 型號： | SYM53C180 |
| 廠商： | LSI Corporation |
| 英文描述： | Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴(kuò)展器) |
| 中文描述： | 個Ultra3 SCSI總線擴(kuò)展（Ultra2的SCSI總線擴(kuò)展器） |
| 文件頁數(shù)： | 22/78頁 |
| 文件大?。?/td> | 1073K |
| 代理商： | SYM53C180 |
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2-4
Functional Descriptions
LVD Link technology is based on current drive. Its low output current
reduces the power needed to drive the SCSI bus. Therefore, the I/O
drivers can be integrated directly onto the chip. This reduces the cost
and complexity compared to traditional (high power) differential designs.
LVD Link lowers the amplitude of noise reflections and allows higher
transmission frequencies.
The LVD Link transceivers in side A and side B operate in the LVD or
SE modes. The SYM53C180 automatically detects the type of signal
connected, based on the voltages detected by A_DIFFSENS and
B_DIFFSENS.
2.1.2 Retiming Logic
The SCSI signals, as they propagate from one side of the SYM53C180
to the other side, are processed by logic circuits that retime the bus
signals, as needed, to guarantee or improve the required SCSI timings.
The retiming logic is governed by the State Machine Controls that keep
track of SCSI phases, the location of initiator and target devices, and
various timing functions. In addition, the retiming logic contains
numerous delay elements that are periodically calibrated by the Precision
Delay Control block in order to guarantee specified timing such as output
pulse widths, setup and hold times, and other elements.
When a synchronous negotiation takes place between devices, a nexus
is formed, and the corresponding information on that nexus is stored in
the on-chip RAM. This information remains in place until a chip reset,
power down, or renegotiation occurs. This enables the chip to make
more accurate retiming adjustments.
2.1.3 Precision Delay Control
The Precision Delay Control block provides calibration information to the
precision delay elements in the Retiming Logic block. This calibration
information provides precise timing as signals propagate through the
device. As the SYM53C180 voltage and temperature vary over time, the
Precision Delay Control block periodically updates the delay settings in
the Retiming Logic. The purpose of these updates is to maintain constant
and precise control over bus timing.
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