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參數(shù)資料
| 型號： | SYM53C180 |
| 廠商： | LSI Corporation |
| 英文描述： | Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴展器) |
| 中文描述： | 個Ultra3 SCSI總線擴展（Ultra2的SCSI總線擴展器） |
| 文件頁數(shù)： | 27/78頁 |
| 文件大?。?/td> | 1073K |
| 代理商： | SYM53C180 |
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Interface Signal Descriptions
2-9
2.1.7.5 Reset Control (SRST)
A_SRST and B_SRST are also passed from the source to the load bus.
This output has pull-down control for an open collector driver. The reset
signals are processed in this sequence:
1.
The input signal is blocked if it is already being driven by the
SYM53C180.
2.
The next stage is a leading edge filter. This ensures that the output
will not switch during a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3.
A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
When the SYM53C180 senses a true mode change on either bus, it
generates a SCSI reset to the opposite bus. For example, when LVD
mode changes to SE mode, a reset occurs.
2.1.7.6 Request and Acknowledge Control (SREQ and SACK)
A_SREQ, A_SACK, B_SREQ, and B_SACK are clock and control
signals. Their signal paths contain controls to guarantee minimum pulse
widths, filter edges, and do some retiming when used as data transfer
clocks. In double transition clocking, both leading and trailing edges are
filtered, while only the leading edge is filtered in single transition clocking.
SREQ and SACK have paths from the A Side to the B Side and from the
B Side to the A Side. The received signal goes through these processing
steps before being sent to the opposite bus:
1.
The asserted input signal is sensed and forwarded to the next stage
if the direction control permits it. The direction controls are developed
from state machines that are driven by the sequence of bus control
signals.
2.
The signal must then pass the test of
not
being regenerated by the
SYM53C180.
3.
The next stage is a leading edge filter. This ensures that the output
does not switch during the specified hold time after the leading edge.
The duration of the input signal determines the duration of the output
after the hold time. The circuit guarantees a minimum pulse rate.
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