參數(shù)資料
型號(hào)： SYM53C180
廠商： LSI Corporation
英文描述： Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴(kuò)展器)
中文描述： 個(gè)Ultra3 SCSI總線擴(kuò)展（Ultra2的SCSI總線擴(kuò)展器）
文件頁數(shù)： 28/78頁
文件大小： 1073K
代理商： SYM53C180
2-10
Functional Descriptions
4.
The next stage passes the signal if it is not a data clock. If SREQ or
SACK is a data clock, it delays the leading edge to improve data
output setup times. The input signal again controls the duration.
5.
This stage is a trailing edge signal filter. When the signal deasserts,
the filter does not permit any signal bounce. The output signal
deasserts at the first deasserted edge of the input signal.
6.
The last stage develops pull-up and pull-down signals with drive and
3-state control.
7.
A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
2.1.7.7 Control/Data, Input/Output, Message, and Attention Controls
(SCD, SIO, SMSG, and SATN)
A_SCD, A_SIO, A_SMSG, A_SATN, B_SCD, B_SIO, B_SMSG, and
B_SATN are control signals that have the following processing steps:
1.
The input signal is blocked if it is being driven by the SYM53C180.
2.
The next stage is a leading edge filter. This ensures the output does
not switch for a specified time after the leading edge. The duration
of the input signal determines the duration of the output.
3.
The final stage develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
4.
A parallel function ensures that bus (transmission line) recovery is for
a specified time after the last signal deassertion on each signal line.
2.1.7.8 Multimode Signal Control
A_SD[15:0], A_SDP[1:0], A_SBSY, A_SSEL, A_SCD, A_SIO, A_SMSG,
A_SREQ, A_SACK, A_SATN, A_SRST, B_SD[15:0], B_SDP[1:0],
B_SBSY, B_SSEL, B_SCD, B_SIO, B_SMSG, B_SREQ, B_SACK,
B_SATN, and B_SRST are all multimode signals. The mode is controlled
by the voltage sensed at the DIFFSENS input. The A and B sides are
independently controlled.
When the correct DIFFSENS voltage selects SE mode, the plus signal
leads are internally tied to ground and the minus SCSI signals are the
SE input/outputs.
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