參數(shù)資料
型號： SYM53C180
廠商： LSI Corporation
英文描述： Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴展器)
中文描述： 個Ultra3 SCSI總線擴展（Ultra2的SCSI總線擴展器）
文件頁數(shù)： 29/78頁
文件大?。?/td> 1073K
代理商： SYM53C180
Interface Signal Descriptions
2-11
When the correct DIFFSENS voltage selects LVD mode, the plus and
minus signal leads are the differential signal pairs.
A transition from any mode to another mode causes a SCSI RST to be
asserted on the opposite SCSI bus as a notification of state change.
2.1.7.9 A and B Differential Sense (A_DIFFSENS and B_DIFFSENS)
These control pins determine the mode of SCSI bus signaling that will
be expected.
For example, if a differential source is plugged into the B Side that has
been configured to run in the differential mode and if a single-ended
source is detected, then the B Side is disabled and no B Side signals
are driven. This protection mechanism is for single-ended interfaces that
are connected to differential drivers.
2.1.7.10 A and B RBIAS (LVD Current Control)
These control pins require a 10 K 1% resistor connected to V
DD
.
2.1.8 Control Signals
This section provides information about the RESET/, WS_ENABLE, and
XFER_ACTIVE pins. It also describes the function of the CLOCK input.
2.1.8.1 Chip Reset (RESET/)
This general purpose chip reset forces all of the internal elements of the
SYM53C180 into a known state. It brings the State Machine to an idle
state and forces all controls to a passive state. The minimum RESET/
input asserted pulse width is 100 ns.
The SYM53C180 also contains an internal Power On Reset (POR)
function that is ORed with the chip reset pin. This eliminates the need
Table 2.2
Mode Sense Control Voltage Levels
Voltage
Mode
-0.35 to +0.5
SE
+0.7 to +1.9
LVD
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