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參數(shù)資料
| 型號(hào)： | STV0196 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK DEMODULATOR AND FEC IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制解調(diào)器和FEC集成電路 |
| 文件頁(yè)數(shù)： | 7/23頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | STV0196 |
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II - ADCINTERFACE
II.1 - M_CLK Master Clock Input
This is the highest frequency clock of the chip, at
twice the symbol frequency; all other clocks are
derived from it.
This clock should be output from an externalVCO
or VCXO,controlled byCLKREC output.
M_CLK divided by 60 is available to the system
(output D60).
II.2 - I and Q Signal Inputs
Those signals are coded on 6 bits, either in 2’s
complement or as positive values : the choice is
programmablevia the Input Configurationregister.
The
π
/2 ambiguityinherentinQPSKissolvedinthe
Error Correction part.
A programmable bit in a mode register allows to
multiply by -1 the data on Q input, in order to
accommodateQPSKmodulationwithanothercon-
vention of rotation sense ; (this is equivalent to a
permutation of I and Q inputs, or a spectral sym-
metry).
III - NYQUIST ROOT FILTER
The I and Q components are filtered by a digital
Nyquist root filter with the following features :
- Input :separateIandQstreams,twosamplesper
symbol.
- Excessbandwidth : 0.35in Mode A.
- The filters may be bypassed ; in this case, the
input flow is connected to the carrier and clock
recoverysection.
Input Configuration Register
(the written value of eachbit is the reset value)
InternalAddress : Hex00
0
0
0
0
0
1
0
0
B
N
o
S
I
-
IV - TIMING RECOVERY
The timing loop comprises an external VCO
or VCXO, running at twice the symbol frequency,
controlledby the output CLKREC ; this signal is a
pulse density modulated output, at the symbol
frequency, and represents the filtered timing
error.
The loop is parametrised by two coefficients : al-
pha_tmg and beta_tmg ; the 12 bit filter output is
converted into a pulse density modulation signal
whichshouldbefilteredbyananaloglowpassfilter
before commanding the VCO.
IV.1 - TimingLoop Registers
Time Constant Register
InternalAddress : Hex0C
Reset Value : Hex45
Istr
Invert
bit
The bit ”Istr” allows to change the polarity of the
output signal, in order to accommodateboth pos-
sibilities of external VCO :
1
0
0
0
1
0
1
alpha_tmg (1 to 6)
beta_tmg (0to 9)
Istr
0
Loop Control
VCO frequency raises when output average
voltage raises
VCO frequency decreases when output
average voltage raises
1
Timing Frequency Register
InternalAddress : Hex0D
Signed number
The value of this register, when the system is
locked,isanimageof thefrequencyoffset;itshould
be as close as possible to 0 in order to have a
symmetriccapturerange;readingitallows optimal
trimmingof the timing VCOrange.
IV.2 - Loop Equations
The external VCO is controlled by the output
CLKREC followedby a low pass filter.
The full analog swing of the output originates a
relative frequency shift of 2
f , dependingon the
characteristics of the external VCO (typically a
fraction of percent).
The frequencyrange is thereforef = f
0
( 1
±
f).
Neglectingthe analog low pass filter on the pulse
modulatedoutput, thisloop may be consideredas
a secondorder loop.
FUNCTIONAL DESCRIPTION
(continued)
STV0196B
7/23
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