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參數(shù)資料
| 型號： | STV0196 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK DEMODULATOR AND FEC IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制解調(diào)器和FEC集成電路 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大小： | 236K |
| 代理商： | STV0196 |
PIN LIST
Pin Number
SIGNAL INPUTS
51, 52, 53, 54, 55, 56
57, 58, 59, 60, 61, 62
48
FRONT END CONTROLS
Pin Name
Type
Pin Description
I [5..0]
Q [5..0]
M_CLK
I
I
I
In Phase Component, at twice the symbol frequency (2Fs).
In QuadratureComponent, at twice the symbol frequency (2Fs).
Master Clock Input, 2Fs. Sampling Clock of the External A toD Converters.
46
44
35
CLKREC
AGC
D60
O
O
O
1 BitControl Signal for the External CLK VCO. Itmust be Low-pass Filtered.
1 Bit Control Signal for the External AGC. It must be Low-pass Filtered.
M_CLK Divided by 60
SIGNAL OUTPUTS
26, 25, 24, 23,
22, 21, 20, 19
D [7..0]
O
Output Data
29
30
33
34
CK_OUT
STR_OUT
D/P
ERROR
O
O
O
O
Output Byte Clock
Output Synchronization Byte Signal
Data/Parity Signal
Output Error Signal. Set in Case of uncorrected Block.
I
2
C MICRO INTERFACE
39
40
SCL
SDA
I
Serial Clock
Serial Data Bus
I/O
OTHER
47
MODE
TEST
I
0 = Mode A, 1 = Mode B
Reserved for Manufacturing Test. It must remain unconnected
1, 2, 5, 6, 13, 14, 15,
16, 17, 18, 63, 64
3, 7, 9, 11, 28, 32,
37, 41, 42, 49
4, 8, 10, 12, 27,
31, 38, 43, 45, 50
36
O
V
SS
I
Ground References
V
DD
I
3.3V Supply
NRES
I
Negative Reset
0
VITERBI DECODER
DEINTERLEAVER
REED SOLOMONDECODER
ENERGY DESCRAMBLER
NYQUIST
FILTER
DEROTATOR
AGC
LOCK
INDICATOR
DCO
TIMING
RECOVERY
CARRIER
OFFSET
MEASURE
CARRIER PHASE
TRACKING LOOP
DIVIDEBY 60
I
2
C BUS
INTERFACE
AGC
D/P
ERROR
STR_OUT
CK_OUT
I[5...0]
Q[5...0]
CLKREC
D60
M_CLK
SCL
SDA
MODE
V
DD
V
SS
D[7..0]
STV0196B
C/N
INDICATOR
0
BLOCK DIAGRAM
STV0196B
3/23
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STV0196B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QPSK/BPSK DEMODULATOR AND FEC IC |
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| STV0289 | 制造商:STMicroelectronics 功能描述: |
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