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參數資料
| 型號： | STV0196 |
| 廠商： | 意法半導體 |
| 英文描述： | QPSK/BPSK DEMODULATOR AND FEC IC |
| 中文描述： | 調制/ BPSK調制解調器和FEC集成電路 |
| 文件頁數： | 14/23頁 |
| 文件大小： | 236K |
| 代理商： | STV0196 |
ABSOLUTE MAXIMUM RATINGS
Maximum limits indicate where permanent device damagesoccur, continuousoperation at these limits is
not intended and should be limited to thoseconditionsspecified insection ”DC ElectricalSpecifications”.
Symbol
V
DD
V
I
V
o
T
stg
T
oper
P
D
Parameter
Value
-0.3 to 4
Unit
V
V
V
o
C
o
C
W
Power Supply (1)
Voltage on Input pins (2)
Voltage on Output pins
Storage Temperature
Operating Ambient Temperature
Power Dissipation
-0.3 to V
DD
+ 0.3
-0.3 to V
DD
+0.3
-40 to +150
-10 to +85
1.5
Notes :
1. All V
to be tied together
2. SCL, SDA, NRES Pins can be tied to 5V
±
10% with an impedance
≥
2k
(remark in these conditions the input leakage current
becomes higher than 10
μ
A).
0
DC ELECTRICALCHARACTERISTICS
(V
DD
= 3.3V, T
amb
= 25
o
C unless otherwise specified)
Symbol
V
DD
Parameter
Test conditions
Min.
3.0
3.15
Typ.
3.3
3.3
300
Max.
3.6
3.45
480
Unit
V
V
mA
Operating Voltage
0
o
C
≤
T
oper
≤
70
o
C
0
o
C < T
oper
< 85
o
C, M_CLK
≤
55MHz
C
LOAD
= 20pF on all outputs,
M_CLK = 60MHz
M_CLK = 60MHz
I
DD
Average Power Supply Current
V
IL
V
IH
V
IL
V
IH
I
LK
C
IN
V
OL
V
OH
Input Logic Low Voltage exceptM_CLK
Input Logic High Voltage except M_CLK
Input Logic Low Voltage for M_CLK
Input Logic High Voltage for M_CLK
Input Leakage Current
Input Capacitance
Output Logic Low Voltage
Output Logic High Voltage
-0.3
2.0
-0.3
2.2
0.8
3.6
0.8
3.6
10
V
V
V
V
μ
A
pF
V
V
M_CLK = 60MHz
V
IN
= 0V and V
DD
3.5
C
= 20pF, I
LOAD
= 2mA,
M_CLK = 60MHz
2.4
0.5
Note :
This product doesn’twithstand the MIL883C Norm at 2kV,but onlyat 1.5kV(all V
DD
tied together).
0
TIMING CHARACTERISTICS
Symbol
PRIMARY CLOCK (see Figure4)
t
M_CLK
Master Clock Period
Parameter
Min.
Typ.
Max.
Unit
0
o
C
≤
T
oper
≤
70
o
C
0
o
C < T
oper
< 85
o
C
16.6
18.2
6
6
ns
ns
ns
ns
ns
ns
t
HIGH
t
LOW
t
R
t
F
Clock High Time
Clock Low Time
Clock Rising Edge
Clock FallingEdge
4
4
I[5:0],Q[5:0] INPUT SPECIFICATIONS (see Figure 5)
t
SU
I,Q stable before M_CLK
t
H
I,Q stable after M_CLK
D60 OUTPUT CHARACTERISTICS (see Figure 6)
t
60
D60 period
4
4
ns
ns
(Tm_clk * 60)
- 10
(Tm_clk*60)
+10
ns
D[7:0],D/P,CK_OUT,STR_OUT,ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in register RS ( adr = 0x0A)(see Figure 7)
t
CKSU
D[7:0],D/P,STR_OUT,ERRORstablebefore CK_OUT Falling Edge
t
CKH
D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Falling Edge
Bit RS1 = 0 in register RS ( adr = 0x0A)(see Figure 8)
t
CKSU
D[7:0],D/P,STR_OUT,ERRORstable before CK_OUT Rising Edge
t
CKH
D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Rising Edge
32
32
ns
ns
32
32
ns
ns
0
STV0196B
14/23
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