- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382568 > STV0196 (意法半導(dǎo)體) QPSK/BPSK DEMODULATOR AND FEC IC PDF資料下載
參數(shù)資料
| 型號： | STV0196 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK DEMODULATOR AND FEC IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制解調(diào)器和FEC集成電路 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 236K |
| 代理商： | STV0196 |
VIII - AGC CONTROL
The modulusoftheinputiscomparedtoaprogram-
mable threshold; the difference is scaled by the
AGC coefficient,then integrated; the result is con-
verted into a pulse density modulation signal to
drive theAGC output; it maybe filteredbyasimple
analogue filterto control the gain command of any
amplifier before the Ato D converter.
The 8 integrator MSB’s may be read or written at
any time by the micro; when written, the LSB’s are
reset. The integrator value is the level of the AGC
output, after low pass filtering ;it givesan image of
the inputsignal power,whateverthis signal is,and
can be used to point the antenna.
The coefficientmay be reset by programmation; in
that case, the AGC reduces to a programmable
voltage synthesiser.
The AGC reference level ”m” value impacts the
value of the following functions:
- carrierto noise indicator(see paragraph VII)
- the carrierloop (seeparagraph V.2)
- the timing loop (paragraphIV.2)
- carrieroffset evaluator (paragraphVI)
Control Registers
InternalAddresses: Hex11
Iagc
0
0
1
1
0
0
0
Invert
signal
Reserved
AGC reference
level (”m”)
InternalAddresses: Hex12
AGC integrator value (signed)
(Read/write register)
InternalAddresses: Hex13
0
0
0
0
0
0
1
0
Reserved
G[2..0] :
AGC coefficient
The 8bit signedvalue inthe integratoristhe image
of the AGC output; reading this value gives an
image of the RF signal power.
Aconstant error on the modulusleads to arampat
the outputof the integrator with value :
AGC_Int = 2
AGC_Coeff-16
.error
As a consequence,forthe reset conditions,a con-
stant signal of nullvalue (error = 24) shouldcause
the outputAGCduty cycle to go from 100%to 0%
in 2
22
symbolperiods, or 8.7ms at 20MBauds.
If Iagc is set, the sign of the integratoris inverted.
IX-VITERBIDECODERANDSYNCHRONIZATION
The convolutives codes are generated by the
polynoms Gx = 171
oct
and Gy = 133
oct
.
The Viterbi decodercomputesfor each symbolthe
metrics of the four possible paths, proportional to
the square of the Euclidian distance between the
receivedI andQ and the theoreticalsymbol value.
The puncturerate and phaseare estimatedon the
error rate basis.
Five rates are allowed and may be enabled/dis-
abled through register programming :
1/2, 2/3, 3/4,5/6,7/8.
In ModeB, 7/8 is replacedby 6/7.
For each enabled rate, the current error rate is
compared to a programmable threshold; if it is
greater,anotherphase(oranotherrate)istrieduntil
the good rate is obtained.
A programmable hysteresis is added to avoid to
loose the phaseduring short term perturbation.
The rate may also be imposed by the external
software, and the phase is incremented only on
micro request ; the error rate may be read at any
time in order to use other algorithm than imple-
mented.
The decoder is accessed via a set of 9 registers :
ThresholdRegisters
(VTH0 to VTH4)
InternalAddress : Hex1 (VTH0) to 5 (VTH4)
Reset Value : Hex20
Threshold
Value
rate 1/2
rate 2/3
rate 3/4
rate 5/6
rate 7/8
or6/7
VTH0 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
VTH1 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
VTH2 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
VTH3 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
VTH4 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
For eachregister, bits 6to 0representan error rate
threshold : the average number of errors happen-
ing during 256 bit periods;the maximumprogram-
mable value is 127/256 (higher error rates are of
no practicaluse).
Puncture Rate Enable register
InternalAddress : Hex09
Reset Value : Hex10 (Mode A)
0
0
0
E4
E3
E2
E1
E0
E4: enablePuncturedRate7/8(ModeA)or6/7(ModeB)
E3: enable PuncturedRate 5/6
E2: enable PuncturedRate 3/4
E1: enable PuncturedRate 2/3
E0: enable Basic Rate 1/2
FUNCTIONAL DESCRIPTION
(continued)
STV0196B
11/23
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STV0680-001 | Low Cost Digital Camera (LCDC) Chipset |
| STV0680A-002 | Low Cost Digital Camera (LCDC) Chipset |
| STV0680B-001 | THERMOMETER, SURFACE; RoHS Compliant: NA |
| STV0680B-003 | ULTRASONIC LEAK DETECTOR |
| STV0680 | DUAL-MODE DIGITAL CAMERA CHIPSET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STV0196B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QPSK/BPSK DEMODULATOR AND FEC IC |
| STV02 | 功能描述:DIP 開關(guān)/ SIP 開關(guān) 2 POS SIP SWITCH RoHS:否 制造商:Omron Electronics 位置數(shù)量:10 開關(guān)類型:DIP 執(zhí)行器:Rotary 端子節(jié)距:2.54 mm 觸點形式: 端接類型:Solder Pin 電流額定值:100 mA 電壓額定值 DC: 工作溫度范圍: 安裝:Through Hole |
| STV0288 | 制造商:STMicroelectronics 功能描述: 制造商:STMicroelectronics 功能描述:SADA_(REG)DVB-S DEMODULATOR |
| STV0288-NIM | 制造商:STMicroelectronics 功能描述:EVALUATION KIT FOR DVB SATELLITE COMMUNICATIONS. - Bulk |
| STV0289 | 制造商:STMicroelectronics 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。