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參數(shù)資料
| 型號(hào)： | STV0196 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK DEMODULATOR AND FEC IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制解調(diào)器和FEC集成電路 |
| 文件頁(yè)數(shù)： | 15/23頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | STV0196 |
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I
2
C BUSCHARACTERISTICS
(see Figure 9)
Symbol
V
IL
V
IH
V
OL
V
OH
I
LK
C
IN
I
OL
t
SP
Parameter
Test Conditions
Min.
-0.3
2.0
Typ.
Max.
0.8
5.5
0.5
5.5
10
Unit
V
V
V
V
μ
A
pF
mA
ns
Input Logic Low Voltage
Input Logic High Voltage
Output Logic Low Voltage
Output Logic High Voltage
Input Leakage Current
Input Capacitance
Output SinkCurrent
Pulse Width of Spikes which must be
suppressed by the Input filter
SCL Clock Frequency
Bus Free Time between a STOP and START
Condition
Hold Time (repeated) START Condition. After
this period, the firstclock pulse isgenerated.
Low Period of the SCL Clock
High Period of the SCL Clock
Set-up Time for a repeated START Condition
Set-up Time for STOP Condition
Data Hold Time
Data Set-up Time
Rise and Fall Time of both SDA and SCL
signals
Capacitive Load for each Bus Line
See Note 1
C
= 20pF, I
= 2mA,
M_CLK = 60MHz, see Note 1
V
IN
= 0V to V
DD
, see Note 2
2.4
-10
3.5
10
V
OL
= 0.5V
0
50
f
SCL
t
BUF
0
400
kHz
μ
s
1.3
t
HD,STA
0.6
μ
s
t
LOW
t
HIGH
t
SU,STA
t
SU,STO
t
HD,DAT
t
SU,DAT
t
R
, t
F
1.3
0.6
0.6
0.6
0
100
20 +
0.1 C
B
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
See Note 3
See Note 4
See Note 5
0.9
300
C
B
400
pF
Notes :
1.
An impedance higher than 2k
is required when SDA and SCL are tiedto a 5V
±
10% voltage line.
Leakage current exceeds
±
10
μ
A whenSDA and SCL are tied toa 5V
±
10% line.
A device must internally provide a holdtime ofat least 300ns forthe SDA signal (refered to the V
IH Min.
of theSCL signal) in order
to bridge the undefined region of the falling edge of SCL.
The maximum tHD,DAT has only to be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
A fast-mode I
C bus device can be used in a standard-mode I
C bus system, but the requirement t
≥
250nsmust then be
met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R Max.
+ t
SU,DAT
= 1000 +250 = 1250ns
(according to the standard-mode I
C bus specification) before the SCL line is released.
C
B
= total capacitance of one bus line in pF.
2.
3.
4.
5.
0
STV0196B
15/23
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