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參數(shù)資料
| 型號(hào)： | STA400A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | XMRADIO SDARS CHANNEL DECODER |
| 中文描述： | XMRADIO衛(wèi)星數(shù)字收音機(jī)信道解碼器 |
| 文件頁(yè)數(shù)： | 27/117頁(yè) |
| 文件大?。?/td> | 910K |
| 代理商： | STA400A |
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STA400A
2
REGISTER MAP
Table 1. Register Classes
pr:
pri:
wrt:
Write and read register plus trigger output signal when write access.
rt:
Read only register plus trigger output signal when read access.
int:
This register class always consists out of a status and mask register. The status register stores interrupt
signals from CDEC. The mask registers determines if an interrupt signal should generate an irq_out signal
or not.
trt:
A transparent register does not exists physically in the register map. The register map pipelines the
information to the CDEC register. The register operates as a normal write/read register in the register
map.
Note:
The pr and rt register classes must be read with the random address read mode only. Sequential read
mode is not allowed.
Event counter. (increments if input =1 and will be reset after read access to preset value)
Event counter like pr-register, plus trigger output signal if maximum is arrived.
Table 2. Base Address List
Abbreviations
Name of Register Class
wr
write and read
r
read
rt
read plus en-trigger
pr
preset when read
pri
preset when read plus trigger signal
wrt
write and read plus trigger signal
int
interrupt register pair
trt
transparent
Base Address (hex)
Block
00
Satellite Demodulators (SatDem1 + SatDem2)
01
Terrestrial Demodulator (Section 1)
02
TDM (Section 1)
03
FEC
04
IF Sampling and Control Interface
05
PC Bitstream Interface
06
TDM (Section 2)
07
Terrestrial Demodulator (Section 2)
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