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參數(shù)資料
| 型號： | STA400A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | XMRADIO SDARS CHANNEL DECODER |
| 中文描述： | XMRADIO衛(wèi)星數(shù)字收音機(jī)信道解碼器 |
| 文件頁數(shù)： | 19/117頁 |
| 文件大?。?/td> | 910K |
| 代理商： | STA400A |
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19/117
STA400A
Figure 11. Timing Error Detector Gain
Timing Loop Filter
The timing loop filter is a first order IIR filter with two programmable parameters, one for the proportional and
the other for the integral correction, as shown in fig.6. The output of the integrator, that produces a frequency
control term, is summed with the weighted timing error in the proportional path and then sent to the timing NCO
to close the timing tracking loop.
The proportional gain alpha and the integral gain beta of the filter are programmable by the registers ALFATIM
and BETATIM respectively. The integral gain is set by a mantissa and exponent as given by:
beta = beta_m x 2
(beta_e)
where beta_m, the mantissa, is a 5-bit integer value set in the five LSBs of the BETATIM register (beta_m=BE-
TATIM[4:0]) and beta_e, the exponent, is a 3-bit integer set in the three MSBs of the BETATIM register
(beta_e=BETATIM[7:5]).
The proportional gain is an integer value set in the ALFATIM register with a range from 0 to 255 (alpha=ALFA-
TIM[7:0]). The TIMINTG register collects the 8 MSBs of the filter integrator and may be read or written at any
time by the system controller. When the register is written the integrator LSBs are reset.
A limiter is provided on the filter integrator to limit the frequency sweep of the timing NCO. After a drop-out or
during the unlock condition, the frequency uncertainty of the timing NCO (that produces a symbol slip on the
demodulated data) can be controlled setting the maximum number of bit in the timing integrator. This value is
set in the LIMITER block by the TIMLPF_LENGTH parameter (see TIMLPF_CTRL register). The limiter peak-
to-peak range can take 8 values from 8-bits to 20-bits corresponding to a frequency shift from 182Hz to 7.5KHz
respectively.
Timing Integrator Control
This block operates on the timing loop integrator. During a very long drop-out or when no signal is applied to the
demodulator input, the timing loop integrator may drift up to the saturation value. As the signal is applied again
or after the drop-out event, it is possible that the integrator remains in saturation for a long period causing a very
slow symbol re-acquisition time. The TimintgCtrl block recognizes this event and sends a reset to the integrator
register to speed-up the re-acquisition phase.
The flow diagram of the TimintgCtrl block Finite State Machine (FSM) is depicted in fig.12. The FSM parameters
and the block enable/disable command are set in the TIMLPF_CTRL register
0
2
4
6
8
10
12
14
16
18
20
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
TED Gain
C/N (dB)
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