參數(shù)資料
型號: STA400A
廠商: 意法半導體
英文描述: XMRADIO SDARS CHANNEL DECODER
中文描述: XMRADIO衛(wèi)星數(shù)字收音機信道解碼器
文件頁數(shù): 20/117頁
文件大?。?/td> 910K
代理商: STA400A
STA400A
20/117
Figure 12. TimingCtrl FSM Flow Diagram
Timing Loop Equations
The timing recovery is fully digital and comprises two blocks working at symbol rate: the Timing Error Detector
and the Loop Filter and two blocks working at clock rate: the Timing NCO and the Nyquist/Interpolator filters
(see fig.6).
The loop is parametrised by the coefficients alpha and beta given in the registers ALFATIM and BETATIM re-
spectively. The timing loop is a second order loop whose natural frequency f
n
and damping factor
ξ
may be cal-
culated by the following formulas:
where alpha is set in the ALFATIM register and beta in the BETATIM register, K
d
is the TED gain as shown in
fig.11 and m is the reference level of the AGC2 loop (see AGC2REF register).
For example, to set the loop natural frequency to 126Hz with the default value for m=AGC2REF (90dec, 5Ahex)
and K
d
= 0.56 (noise free value), the above equation solved for beta gives:
alpha can be chosen to have a damping factor equal to 0.7:
The register ALFACAR can be programmed with 5 (Dec) and the register BETACAR can be programmed with
the parameter BETA_E=0 and BETA_M=14 (Dec).
demodulator
unlocked (LOCK=1)
demodulator locked
(LOCK=0)
demodulator unlocked for a time less than
a fixed value (TIMINTG_CLR_WIN)
demodulator
unlocked
demodulator unlocked for a time equal to a fixed
value (TIMINTG_CLR_WIN)
Reset Time Counter
Clear Releasing in the Time Loop
Filter Integrator
Time Counter Active
Time Counter Reset
Time Loop Filter Integrator Cleared
demodulator locked (LOCK=0)
or
TIMING_CLR_EN=0
f
n
4.76 mK
d
beta [Hz]
ζ
0.075 alpha
mK
d
beta
------------
=
=
beta
f
2
22.6576mK
d
---------------------------------
13.90
=
=
alpha
0.075
--------------
mK
d
------------
4.9
=
=
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