參數(shù)資料
型號： STA400A
廠商： 意法半導(dǎo)體
英文描述： XMRADIO SDARS CHANNEL DECODER
中文描述： XMRADIO衛(wèi)星數(shù)字收音機(jī)信道解碼器
文件頁數(shù)： 13/117頁
文件大?。?/td> 910K
代理商： STA400A
13/117
STA400A
The carrier lock indication of the satellite and the terrestrial demodulators, and the status of the FEC Terrestrial-
Satellite combining may be read in the STATUS1 register described in section 2.6.
1.2 SATELLITE DEMODULATION
The satellite signals are demodulated by two QPSK demodulators, one tuned to the East satellite and the other
to the West satellite. The two QPSK demodulators are identical and include quadrature demodulation, carrier
and timing recovery and tracking, frequency sweep generation, Nyquist Root Raised Cosine filtering with 15%
roll-off, digital AGC, lock indication and carrier to noise estimation.
Figure 6. Satellite Demodulator Block Diagram
The architecture of one QPSK demodulator is depicted in fig.6. The input signal, sampled at 23.92 MHz and
quantized on 8 bits, is multiplied by the sine an cosine functions to obtain the In-phase and the Quadrature com-
ponent of the transmitted symbols. The demodulated QPSK signal is affected by the phase and frequency error
due to oscillator inaccuracies and frequency shift. These errors are removed by the carrier tracking loop by
means of a Phase/Frequency Detector, a loop filter and an NCO. The symbol tracking loop removes the phase
and frequency uncertainties in the symbols: instead of controlling the sampling clock phase, the timing error de-
tector adjusts, using the timing NCO, the impulse response phase of the two interpolator filters.
To enhance the performace of the demodulator in presence of a signal dropout, the carrier and symbol loops
are controlled by the CarrierNullOffset and the TimingCtrl blocks. The first operates on the Carrier NCO and
Carrier Loop Filter, the latter on the Timing Loop Filter.
An internal ramp generator (FreqSweep) is used to help the carrier loop during the acquisition phase. The fre-
quency sweep is stopped by the lock detector output whenever a lock condition is reached.
The phase ambiguity introduced by the demodulation process and the frame synchronization are resolved in the TDM
Decoding block using the Master Frame Preamble (MFP) and the Fast Syncronization Preamble (FSP).
SYMBOL
CLOCK
LOCK_Sx
pin 37/38
N
IOUT
QOUT
RRC
INTERPOLATOR
FILTER
RRC
INTERPOLATOR
FILTER
C/N
ESTIM
uP
AGC2REF
+
-
AGC2BETA
L
R
AGC2INTG
T
AGC2 LOOP
I +Q
2
2
SYMFREQ
REG
TIMING NCO
uP
uP
uP
uP
uP
uP
TIMINTG
CTRL
FREQ
SWEEP
CARRIER
NULL
OFFSET
DISABLE
uP
CLEAR
LOCK
DETECT
PHASE
ERROR
DETECTOR
TIMING
ERROR
DETECTOR
uP
SIN/COS
ROM
QCHS
I/Q MIXER - CARRIER NCO
REG
IFFREQ
REG
REG
CARFREQ
uP
FROM
IF SAMPLING
uP
+
+
L
R
BETA_M
uP
L
uP
CARINTG
uP
ALPHACAR
R
uP
BETA_E
CARRIER LOOP FILTER
BETACAR
+
+
L
R
BETA_M
uP
L
uP
TIMINTG
uP
ALFATIM
R
uP
BETA_E
TIMING LOOP FILTER
BETATIM
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