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參數(shù)資料
| 型號(hào)： | STA400A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | XMRADIO SDARS CHANNEL DECODER |
| 中文描述： | XMRADIO衛(wèi)星數(shù)字收音機(jī)信道解碼器 |
| 文件頁(yè)數(shù)： | 18/117頁(yè) |
| 文件大?。?/td> | 910K |
| 代理商： | STA400A |
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STA400A
18/117
The frequency sweep operation is controlled by the RAMPCTRL register. The parameter SWSTEP can take 0
or 1 values and STEPPER can be programmed in the range 0 to 15 decimal.
The maximum peak-to-peak frequency sweep range is 373.75KHz. The sweep direction can be positive or neg-
ative depending on the bit-6 of the RAMPCTRL register. The sweep always starts from the zero value; when
the upper limit is reached, the sweep continues with the lower one if the positive slope is set and viceversa
when the negative slope is selected.
This frequency sweep block can be switched on or off setting the SWON parameter to 1 or 0 respectively. When
SWON=0 the output value of the ramp is null.
Carrier Lock Detector
The lock detector consists of an up/down counter with saturation driven by a dedicated logic. This circuit moni-
tors the QPSK symbol constellation to decid the counter direction. If the actual symbol is inside the region de-
limited by the equations 2 x I - Q
≥
0 and 2 x Q - I
≥
0 (the lock region) the counter counts up otherwise counts
down. If the demodulator is locked, the number of symbols inside the lock region is greater than the number of
symbols outside and the the counter is driven in the up direction toward the saturation limit. When the counter
output is above a programmable threshold, the lock indicator is set to '0' declaring the lock condition of the car-
rier tracking loop. This threshold is set by the LOCKTHR register.
The lock detector controls the frequency sweep generator, the Carrier Null Offset and TIMING_CTRL circuits.
Timing NCO
The timing NCO is the timing generator for the two interpolator filters (see fig.6). To correct the symbol error,
the impulse response of the interpolator is shifted by an amount of time depending on the phase accumulated
in the timing NCO. It consists of a 25-bit modulo-1 accumulator driven by the output of the timing loop filter. The
5LSBs of the accumulator give the fractional part of the sampling clock used by the interpolator filter to select
the coefficients of the impulse response that cancel the timing error. The integer part, given by the carry bit of
the accumulator, is used to decimate to symbol rate the output of the interpolator/matched filter.
The nominal symbol frequency is set by the SYMFREQ register. The timing loop adjusts this nominal value to
find the optimal symbol phase (maximum open eye condition) and to track the residual symbol frequency offset.
The output of the timing generator is given by
F
o
= (F
sym
+ TED
err
) x F
MCLK
/2
25
where F
sym
= 1.64MHz is the nominal symbol frequency, TED
err
is the filtered timing error detector output and F
MCLK
/
2
25
is the NCO resolution.
For example, to set the symbol frequency to 1.64MHz the SYMFREQ register must be loaded with the value
00231A8B (Hex) equivalent to 2300555 (Dec).
Timing Error Detector
The timing error detector (TED) is based on a one sample per symbol algorithm to compute the timing error
between the demodulated symbol at the matched filter output and the optimum sampling instant. The output of
the detector is given by the following equation:
TED
err
= I
n
x Sgn(I
n-1
) - I
n-1
x Sgn(I
n
) + Q
n
x Sgn(Q
n-1
) - Q
n-1
x Sgn(Q
n
)
This signal is filtered by the timing loop filter and then sent to the timing NCO to close the tracking loop.
The TED Gain (K
d
) characteristic as a function of the Carrier to Noise ratio is given in fig.11. K
d
= 0.56 is the
value for a noise free input signal and may be reduce up to 40% of its maximum value in a low C/N condition.
dt
------
SWSTEP
STEPPER
1
+
---------------------------------------
F
2
2
-----------------
[Hz/s]
=
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