參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 36/178頁
文件大?。?/td> 1097K
代理商： ST92E141K4D1
130/178
ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
PERIPHERAL CONTROL REGISTER 0 (PCR0)
R248 - Read/Write
Register Page: 48
Reset Value: 1000 0011 (83h)
Bit 7 = DTE:
Dead Time Counter Enable.
0: Stop and bypass the Dead Time counter
1: Enable the Dead Time counter
Bit 6 = TCE:
Tacho Counter Enable.
0: Stop Tacho counter and prescaler
1: Start Tacho counter and prescaler
Note: This bit is reset by the counter overflow or
by the Tacho capture when the IMC controller is in
one shot mode.
Bit 5 = PCE:
PWM Counter Enable.
0: Stop PWM Counter and prescaler
1: Start PWM Counter and prescaler
Bit 4 = CTC:
Clear of Tacho Counter.
0: No effect
1: Clear the Tacho Counter (this bit is reset by
hardware)
Bit 3 = CPC:
Clear of PWM Counter.
0: No effect.
1: Clear the PWM Counter (his bit is reset by hard-
ware)
Bit 2 = CMS:
PWM Counter Mode Selection.
0: Classical mode.
1: Zerocentered mode
Bit 1 = UDCS:
Up/Down - status (read only).
This bit is set and cleared by hardware.
0: The PWM Counter is counting down.
1: The PWM Counter is counting up.
Bit 0 = ODCS:
Output Dead Time counter Selec-
tion
0: Select the same signal for both (h, l) outputs
1: Select complementary signal for output (Dead
Time Generator outputs)
PERIPHERAL CONTROL REGISTER 1 (PCR1)
R249 - Read/Write
Register Page: 48
Reset Value: 0000 0000 00h
Bit 7 = Reserved.
Bit 6 = NMIE:
Non Maskable Interrupt Enable
0: When an NMI event occurs on the external pin,
it is sent as is (independently of the NMIL value)
to the ST9 core and has no effect on the IMC
controller.
1: When an NMI event occurs on the external pin,
if it is acknowledged (depending on the NMIL
bit) an interrupt request is sent to the ST9 core
(a high level signal ), the NMI pending bit (NMI
bit in IMCIVR register) is set and the OPE bit is
cleared.
Bit 5 = CCPT:
Clear on Capture of tacho counter
0: no clear on capture
1: clear on capture
Bit 4 = TES:
Tacho Event Selection.
0: Select capture by tacho event signal
1: Select capture by software (STC bit)
Bit 3 = STC:
Software tacho capture
0: No effect
1: Capture the Tacho counter (while TES=1). This
bit is reset by hardware
Bit 2 = TCB:
Tacho Counter Mode
0: Select continuous mode.
1: Select one shot mode (counting starts when
TCE bit is set and stops when a capture or an
overflow event occurs).
Bit 1:0 = TIN[1:0]
Tacho Signal Event Sensitivity
These bits select which Tacho signal event trig-
gers the Tacho Capture register.
Table 25. Tacho Signal Event Sensitivity
70
DTE
TCE
PCE
CTC
CPC
CMS
UDCS ODCS
70
-
NMIE
CCPT
TES
STC
TCB
TIN1
TIN0
TIN1
TIN0
Event
0
No operation
0
1
Falling edge
1
0
Rising edge
1
Rising and falling edges
9
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