參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 27/178頁
文件大小： 1097K
代理商： ST92E141K4D1
122/178
ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
7.4.3.5 Polarity Selection
The Polarity Selection performs a logical comple-
ment of the input signals (Uh, Ul, Vh, Vl, Wh, Wl)
as programmed in the Polarity Selection register.
7.4.3.6 Interrupts
The IMC controller generates 8 interrupt requests
and 1 NMI. Each interrupt request has a separate
vector address. The NMI interrupt is managed by
the ST9 as a Top Level Interrupt.The interrupt pri-
ority is fixed by hardware as listed below:
7.4.4 Tacho Counter Operating mode
The Tacho Counter can work in One Shot mode or
in Continuous mode.
In both Continuous or One Shot mode the Capture
event can be generated by hardware (TACHO Pin)
or by software (STC bit in the PCR1 register) ac-
cording to the value of the TES bit in the PCR1
register.
When the CTC bit in the PCR0 register is set, the
TACHO Counter is cleared (this bit is reset by
hardware).
7.4.4.1 Tacho Counter in One Shot mode
In this operating mode (TCB bit = 1 in the PCR1
register) the Counter does the following:
– Counting is started by setting the TCE bit in the
PCR0 register.
– When a Capture event occurs, counting is
stopped (TCE bit is cleared), the value is cap-
tured and a CPT interrupt is generated (if the
CCPT bit in the PCR1 register is set, the Counter
is cleared).
– When the MSB of Tacho Counter reaches the
Tacho Compare register value, the Counter is
stopped (TCE bit is cleared) and the OTC inter-
rupt is generated.
7.4.4.2 Tacho Counter in Continuous mode
In this operating mode (TCB bit = 0 in the PCR1
register) the Counter does the following:
– Counting is started by setting the TCE bit in the
PCR0 register.
– Every Capture event, the value is captured and
a CPT interrupt is generated (if the CCPT bit in
the PCR1 register is set, the Counter is
cleared).
– When the MSB of Tacho Counter reaches the
Tacho Compare register value, an OTC interrupt
is generated.
7.4.5 IMC Operating mode
The IMC controller can work in two different
modes:
– Hardware Operating mode (DTS bit = 0 in
PRCR2 register)
– Software Operating mode (DTS bit = 1 in PRCR2
register)
In both modes, when the corresponding event oc-
curs, the ADT and the other interrupts are generat-
ed.
When the CPC bit in the PCR0 register is set, the
PWM Counter is cleared (this bit is reset by soft-
ware).
7.4.5.1 IMC Hardware Operating mode
After system reset, the Compare U, V, W and
Compare 0 register values are all “0”.
When the PWM Counter is enabled (by setting the
PCE bit in the PCR0 register) and every time the
Repetition Counter and the PWM Counter reach
“0” value, the Repetition Counter is loaded, the
preload registers are loaded into the Compare reg-
isters and an ADT interrupt is generated.
Note: If an ADT (or any other interrupt) is generat-
ed and the previous one is not completed, the last
one will be lost without any error condition being
issued.
Priority
Interrupt Source
CPU Top Level
Int. priority
NMI: Event on external pin
0 High Priority
ADT: Data transfer (when data is trans-
ferred from the preload registers to the
compare registers)
1
ZPC: PWM Counter Zero Event
2
CM0: PWM Counter Compare 0 Event
3
CPT: Tacho Counter Capture Event
4
CPU: Compare U Event (PWM counter
reached U compare value)
5
CPV: Compare V Event (PWM counter
reached V compare value)
6
CPW: Compare W Event (PWM coun-
ter reached W compare value)
7 Low Priority
OTC: Tacho Counter Overflow
9
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