參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 112/178頁
文件大?。?/td> 1097K
代理商： ST92E141K4D1
39/178
ST92141 - INTERRUPTS
3 INTERRUPTS
3.1 INTRODUCTION
The ST9 responds to peripheral and external
events through its interrupt channels. Current pro-
gram execution can be suspended to allow the
ST9 to execute a specific response routine when
such an event occurs, providing that interrupts
have been enabled, and according to a priority
mechanism. If an event generates a valid interrupt
request, the current program status is saved and
control passes to the appropriate Interrupt Service
Routine (refer to Figure 15).
The ST9 CPU can receive requests from the fol-
lowing sources:
– On-chip peripherals
– External pins
– Top-Level Pseudo-non-maskable interrupt
According to the on-chip peripheral features, an
event occurrence can generate an Interrupt re-
quest which depends on the selected mode.
Up to eight external interrupt channels, with pro-
grammable input trigger edge, are available. In ad-
dition, a dedicated interrupt channel, set to the
Top-level priority, can be devoted either to the ex-
ternal NMI pin (where available) to provide a Non-
Maskable Interrupt, or to the Timer/Watchdog. In-
terrupt service routines are addressed through a
vector table mapped in Memory.
Figure 15. Interrupt Response
n
3.2 INTERRUPT VECTORING
The ST9 implements an interrupt vectoring struc-
ture which allows the on-chip peripheral to identify
the location of the first instruction of the Interrupt
Service Routine automatically.
When an interrupt request is acknowledged, the
peripheral interrupt module provides, through its
Interrupt Vector Register (IVR), a vector to point
into the vector table of locations containing the
start addresses of the Interrupt Service Routines
(defined by the programmer).
Each peripheral has a specific IVR mapped within
its Register File pages.
The Interrupt Vector table, containing the address-
es of the Interrupt Service Routines, is located in
the first 256 locations of Memory pointed to by the
ISR register, thus allowing 8-bit vector addressing.
For a description of the ISR register refer to the
chapter describing the MMU.
The user Power on Reset vector is stored in the
first two physical bytes in memory, 000000h and
000001h.
The Top Level Interrupt vector is located at ad-
dresses 0004h and 0005h in the segment pointed
to by the Interrupt Segment Register (ISR).
With one Interrupt Vector register, it is possible to
address several interrupt service routines; in fact,
peripherals can share the same interrupt vector
register among several interrupt channels. The
most significant bits of the vector are user pro-
grammable to define the base vector address with-
in the vector table, the least significant bits are
controlled by the interrupt module, in hardware, to
select the appropriate vector.
Note: The first 256 locations of the memory seg-
ment pointed to by ISR can contain program code.
3.2.1 Divide by Zero trap
The Divide by Zero trap vector is located at ad-
dresses 0002h and 0003h of each code segment;
it should be noted that for each code segment a
Divide by Zero service routine is required.
Warning. Although the Divide by Zero Trap oper-
ates as an interrupt, the FLAG Register is not
pushed onto the system Stack automatically. As a
result it must be regarded as a subroutine, and the
service routine must end with the RET instruction
(not IRET).
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
IRET
INSTRUCTION
INTERRUPT
VR001833
CLEAR
PENDING BIT
1
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