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參數(shù)資料
| 型號： | ST92E141K4D1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32 |
| 封裝： | WINDOWED, SHRINK, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 147/178頁 |
| 文件大小： | 1097K |
| 代理商： | ST92E141K4D1 |
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
CLOCK FLAG REGISTER (CLK_FLAG)
R242 -Read/Write
Register Page: 55
Reset Value: 0100 1000 after a Watchdog Reset
Reset Value: 0010 1000 after a Software Reset
Reset Value: 0000 1000 after a Power-On Reset
WARNING: If this register is accessed with a logi-
cal instruction, such as AND or OR, some bits may
not be set as expected.
WARNING: If you select the CK_AF as system
clock and turn off the oscillator (bits R240.2 and
R242.4 at 1), and then switch back to the XT clock
by resetting the R240.2 bit, you must wait for the
oscillator to restart correctly.
Bit 7 = EX_STP:
Stop Mode flag
This bit is set by hardware and cleared by soft-
ware.
0: No Stop condition occurred
1: Stop condition occurred
Bit 6 = WDGRES:
Watchdog reset flag.
This bit is read only.
0: No Watchdog reset occurred
1: Watchdog reset occurred
Bit 5 = SOFTRES:
Software Reset Flag.
This bit is read only.
0: No software reset occurred
1: Software reset occurred (HALT instruction)
Bit 4 = XTSTOP:
Oscillator Stop Enable.
0: Xtal oscillator stop disabled
1: The Xtal oscillator will be stopped as soon as
the CK_AF clock is present and selected,
whether this is done explicitly by the user pro-
gram, or as a result of WFI, if WFI_CKSEL has
previously been set to select the CK_AF clock
during WFI.
WARNING: When the program writes ‘1’ to the
XTSTOP bit, it will still be read as 0 and is only set
when the CK_AF clock is running (CKAF_ST=1).
Take care, as any operation such as a subsequent
AND with ‘ 1’ or an OR with ‘ 0’ to the XTSTOP bit
will reset it and the oscillator will not be stopped
even if CKAF_ST is subsequently set.
Bit 3 = XT_DIV16:
CLOCK/16 Selection
This bit is set and cleared by software. An interrupt
is generated when the bit is toggled.
0: CLOCK2/16 is selected and the PLL is off
1: The input is CLOCK2 (or the PLL output de-
pending on the value of CSU_CKSEL)
WARNING: After this bit is modified from 0 to 1,
take care that the PLL lock-in time has elapsed be-
fore setting the CSU_CKSEL bit.
Bit 2 = CKAF_ST: (Read Only)
If set, indicates that the alternate function clock
has been selected. If no clock signal is present on
the CK_AF pin, the selection will not occur. If re-
set, the PLL clock, CLOCK2 or CLOCK2/16 is se-
lected (depending on bit 0).
Bit 1= LOCK:
PLL locked-in
This bit is read only.
0: The PLL is turned off or not locked and cannot
be selected as system clock source.
1: The PLL is locked
Bit 0 = CSU_CKSEL:
CSU Clock Select
This bit is set and cleared by software. It also
cleared by hardware when:
– bits DX[2:0] (PLLCONF) are set to 111;
– the quartz is stopped (by hardware or software);
– WFI is executed while the LPOWFI bit is set;
– the XT_DIV16 bit (CLK_FLAG) is forced to ‘0’.
This prevents the PLL, when not yet locked, from
providing an irregular clock. Furthermore, a ‘0’
stored in this bit speeds up the PLL’s locking.
0: CLOCK2 provides the system clock
1: The PLL Multiplier provides the system clock.
NOTE: Setting the CKAF_SEL bit overrides any
other clock selection. Resetting the XT_DIV16 bit
overrides the CSU_CKSEL selection (see Figure
70
EX_
STP
WDG
RES
SOFT
RES
XTSTOP
XT_
DIV16
CKAF_
ST
LOC
K
CSU_
CKSEL
1
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