參數(shù)資料
型號(hào)： ST7PDALIF2M6
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI
中文描述： 8位單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，定時(shí)器，SPI和大理微控制器
文件頁(yè)數(shù)： 71/141頁(yè)
文件大?。?/td> 2175K
代理商： ST7PDALIF2M6
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ST7DALI
71/141
DALI COMMUNICATION MODULE
(Cont’d)
11.4.3 DALI Standard Protocol
The DALI protocol uses the bi-phase Manchester
asynchronous serial data format. All the bits of the
frame are bi-phase encoded except the two stop
bits.
■
The transmission rate is about 1.2 kHz. The bi-
phase bit period is 833.33 us ±10%.
■
A forward frame consists of 19 bi-phase
encoded bits:
– 1 start bit (0->1: logical ’1’)
– 1 address byte (8-bit address)
– 1 data byte (8-bit data)
– 2 high level stop bits (no change of phase)
■
A backward frame consists of 11 bi-phase
encoded bits:
– 1 start bit (0->1: logical ’1’)
– 1 data byte (8-bit data)
– 2 high level stop bits (no change of phase)
A forward frame consists of 19 bi-phase encoded
bits: 1 start bit (logical ’1’), 1 address byte and 1
data byte. The frame is terminated by 2 stop bits
(idle). The stop bits do not contain any change of
phase.
A backward frame consists of 11 bi-phase encod-
ed bits: 1 start bit (logical ’1’) and 1 data byte. The
frame is terminated by 2 stop bits (idle). The stop
bits do not contain any change of phase.
The transmission rate, expressed as a bandwidth,
is specified at 1.2 kHz for the forward channel and
for the backward channel.
The settling time between two subsequent forward
frames is 9.17 ms (minimum).
The settling time between forward and backward
frames is between 2.92 ms and 9.17 ms. If a back-
ward frame has not been started after 9.17 ms,
this is interpreted as "no answer".
In the event of code violation, the frame is ignored.
After a code violation has occurred, the system is
ready again for data reception.
Figure 42. DALI Standard Frame
a7
d7
a6
a5
a4
a3
a2
a1
a0
d6
d5
d4
d3
d2
d1
d0
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
2T
4T
stop bits
start bit
address byte
data byte
FORWARD FRAME
d7
d6
d5
d4
d3
d2
d1
d0
2T
2T
2T
2T
2T
2T
2T
2T
2T
start bit
data byte
BACKWARD FRAME
stop bits
4T
BI-PHASE LEVELS
Logical ’1’
Logical ’0’
2T
2T
2T = 833.33 us ±10%
1
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