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參數(shù)資料
| 型號： | ST7PDALIF2M6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI |
| 中文描述： | 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，定時器，SPI和大理微控制器 |
| 文件頁數(shù)： | 67/141頁 |
| 文件大?。?/td> | 2175K |
| 代理商： | ST7PDALIF2M6 |
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ST7DALI
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LITE TIMER
(Cont’d)
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
11.3.4 Low Power Modes
11.3.5 Interrupts
Note:
The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 =
TB2IE
Timebase 2 Interrupt enable
.
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 0 =
TB2F
Timebase
2
Interrupt Flag
.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
LITE
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
TIMER
AUTORELOAD
REGISTER
Bits 7:0 =
AR[7:0]
Counter 2 Reload Value.
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
Mode
Description
No effect on Lite timer
(this peripheral is driven directly
by f
OSC
/32)
No effect on Lite timer
SLOW
WAIT
ACTIVE-HALT No effect on Lite timer
HALT
Lite timer stops counting
Interrupt
Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Active
Halt
Exit
from
Halt
Timebase 1
Event
Timebase 2
Event
IC Event
TB1F
TB1IE
Yes
Yes
No
TB2F
TB2IE
No
No
ICF
ICIE
Yes
No
No
7
0
0
0
0
0
0
0
TB2IE
TB2F
7
0
AR7
AR7
AR7
AR7
AR3
AR2
AR1
AR0
1
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